{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,21]],"date-time":"2026-01-21T08:16:53Z","timestamp":1768983413201,"version":"3.49.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T00:00:00Z","timestamp":1740441600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T00:00:00Z","timestamp":1740441600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100006129","name":"Funda\u00e7\u00e3o para a Ciencia e a Tecnologia","doi-asserted-by":"publisher","award":["2022.04020.PTDC"],"award-info":[{"award-number":["2022.04020.PTDC"]}],"id":[{"id":"10.13039\/100006129","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,2,25]]},"DOI":"10.1109\/lascas64004.2025.10966239","type":"proceedings-article","created":{"date-parts":[[2025,4,22]],"date-time":"2025-04-22T17:37:30Z","timestamp":1745343450000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Dynamic Reconfigurable FPU for Next-Generation Transprecision Computing"],"prefix":"10.1109","author":[{"given":"Guilherme","family":"Dias","sequence":"first","affiliation":[{"name":"Escola Politécnica, Universidade de São Paulo,Brasil"}]},{"given":"Lu\u00eds","family":"Crespo","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Supzrior Técnico, Universidade de Lisboa,Portugal"}]},{"given":"Pedro","family":"Tomas","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Supzrior Técnico, Universidade de Lisboa,Portugal"}]},{"given":"Nuno","family":"Roma","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Supzrior Técnico, Universidade de Lisboa,Portugal"}]},{"given":"Nuno","family":"Neves","sequence":"additional","affiliation":[{"name":"INESC-ID, Instituto Supzrior Técnico, Universidade de Lisboa,Portugal"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.14529\/jsfi170206"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2019.00023"},{"key":"ref3","article-title":"Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point","volume-title":"in Proceedings of the 34th International Conference on Neural Information Processing Systems, ser. NIPS\u201920","author":"Rouhani"},{"key":"ref4","author":"Wang","year":"2019","journal-title":"Bfloat16: The secret to high performance on cloud tpus"},{"key":"ref5","author":"Jouppi","year":"2017","journal-title":"In-datacenter performance analysis of a tensor processing unit"},{"key":"ref6","first-page":"1421","article-title":"Deep positron: A deep neural network using the posit number system","volume-title":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Carmichael","year":"2018"},{"key":"ref7","volume-title":"IEEE Working Group P3109 Interim Report on 8-bit Binary Floating-point Formats","year":"2024"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176987"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2019.00022"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3044752"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3160191"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2895031"},{"key":"ref13","author":"Waterman","year":"2021","journal-title":"RISC-V \u201cV\u201d Vector Extension"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-021-01687-7"},{"key":"ref15","author":"Hauser","year":"2018","journal-title":"Berkeley testfloat"}],"event":{"name":"2025 IEEE 16th Latin America Symposium on Circuits and Systems (LASCAS)","location":"Bento Gon\u00e7alves, Brazil","start":{"date-parts":[[2025,2,25]]},"end":{"date-parts":[[2025,2,28]]}},"container-title":["2025 IEEE 16th Latin America Symposium on Circuits and Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10966227\/10966228\/10966239.pdf?arnumber=10966239","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T05:05:44Z","timestamp":1745384744000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10966239\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2,25]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/lascas64004.2025.10966239","relation":{},"subject":[],"published":{"date-parts":[[2025,2,25]]}}}