{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T07:56:43Z","timestamp":1764835003837,"version":"3.46.0"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:00:00Z","timestamp":1761609600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:00:00Z","timestamp":1761609600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,28]]},"DOI":"10.1109\/sbac-pad66369.2025.00013","type":"proceedings-article","created":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T18:39:34Z","timestamp":1764787174000},"page":"24-34","source":"Crossref","is-referenced-by-count":0,"title":["MIDAS: A Mapping Infrastructure for Configurable, Data-Streaming Based Domain Specific Accelerators"],"prefix":"10.1109","author":[{"given":"Martim","family":"Bento","sequence":"first","affiliation":[{"name":"Universidade de Lisboa,INESC-ID, Instituto Superior Técnico,Portugal"}]},{"given":"Nuno","family":"Neves","sequence":"additional","affiliation":[{"name":"Universidade de Lisboa,INESC-ID, Instituto Superior Técnico,Portugal"}]},{"given":"Pedro","family":"Tom\u00e1s","sequence":"additional","affiliation":[{"name":"Universidade de Lisboa,INESC-ID, Instituto Superior Técnico,Portugal"}]},{"given":"Nuno","family":"Roma","sequence":"additional","affiliation":[{"name":"Universidade de Lisboa,INESC-ID, Instituto Superior Técnico,Portugal"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3357375"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"ref3","first-page":"184","article-title":"CGRA-ME: A unified framework for CGRA modelling and exploration","volume-title":"2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP)","author":"Chin"},{"key":"ref4","first-page":"642","article-title":"CGRA-ME 2.0: A research framework for next-generation CGRA architectures and CAD","volume-title":"2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","author":"Ragheb"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-15-6401-7_50-1"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3358177"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080256"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00025"},{"key":"ref9","first-page":"115","article-title":"Automatic Generation of Efficient Accelerators for Reconfigurable Hardware","volume-title":"2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)","author":"Koeplinger"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080255"},{"key":"ref11","first-page":"131 788","article-title":"Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey","volume-title":"IEEE Access","volume":"10","author":"Dhilleswararao","year":"2022"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589084"},{"key":"ref13","first-page":"1","article-title":"VecPAC: A vectorizable and precision-aware CGRA","volume-title":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","author":"Tan"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DSD64264.2024.00048"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003702"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322229"},{"article-title":"Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA","volume-title":"Fifth Workshop on Open-Source EDA Technology (WOSET)","author":"Wijerathne","key":"ref17"},{"key":"ref18","first-page":"679","article-title":"Twenty Years of Automated Methods for Mapping Applications on CGRA","volume-title":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","author":"Martin"},{"issue":"3","key":"ref19","first-page":"234","article-title":"Lifetime-sensitive modulo scheduling in a production environment","volume-title":"IEEE Transactions on Computers","volume":"50","author":"Llosa","year":"2001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/micro.1994.717412"},{"key":"ref21","first-page":"1","article-title":"RAMP: Resource-Aware Mapping for CGRAs","volume-title":"2018 55th ACM\/ESDA\/IEEE Design Automation Conference (DAC)","author":"Dave"},{"key":"ref22","first-page":"1","article-title":"DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach","volume-title":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Yin"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3579371.3589081"},{"key":"ref24","first-page":"268","article-title":"PathSeeker: A fast mapping algorithm for CGRAs","volume-title":"2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Balasubramanian"},{"issue":"5","key":"ref25","first-page":"49","article-title":"Compiling for Vector Extensions With Stream-Based Specialization","volume-title":"IEEE Micro","volume":"42","author":"Neves","year":"2022"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS56072.2025.11043244"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228600"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488756"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2655242"}],"event":{"name":"2025 IEEE\/SBC 37th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)","start":{"date-parts":[[2025,10,28]]},"location":"Bonito, Mato Grosso do Sul, Brazil","end":{"date-parts":[[2025,10,31]]}},"container-title":["2025 IEEE\/SBC 37th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11264602\/11264604\/11264642.pdf?arnumber=11264642","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T07:52:05Z","timestamp":1764834725000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11264642\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,28]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/sbac-pad66369.2025.00013","relation":{},"subject":[],"published":{"date-parts":[[2025,10,28]]}}}