{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T12:05:18Z","timestamp":1764331518447,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/sbcci.2002.1137631","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:03:42Z","timestamp":1056575022000},"page":"14-19","source":"Crossref","is-referenced-by-count":8,"title":["A new architecture for 2's complement Gray encoded array multiplier"],"prefix":"10.1109","author":[{"given":"E.","family":"Costa","sequence":"first","affiliation":[]},{"given":"S.","family":"Bampi","sequence":"additional","affiliation":[]},{"given":"J.","family":"Monteiro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/92.645071"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2001.953027"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313942"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/357360.357366"},{"key":"ref14","first-page":"637","article-title":"Modified Booth 1' s Complement and Modulo 2n-1 Multipliers","volume":"2","author":"efstathiou","year":"2000","journal-title":"IEEE International Conference on Electronics Circuits and Systems"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/4.540066"},{"key":"ref16","article-title":"SIS: A System for Sequential Circuit Synthesis","author":"sentovich","year":"1992","journal-title":"Technical Report University of California at Berkeley Memorandum No UCB\/ERL M92\/41"},{"key":"ref17","first-page":"79","article-title":"SLS: An Efficient Switch-Level Timing Simulator Using Min-Max Voltage Waveforms","author":"genderen","year":"1989","journal-title":"VLSI conference"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICWSI.1993.255270"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.857435"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1996.541899"},{"key":"ref6","first-page":"1429","article-title":"On Area-Efficient Low Power Array Multipliers","author":"wang","year":"2001","journal-title":"The 8th IEEE International Conference on Electronics Circuits and Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2001.930100"},{"key":"ref8","article-title":"Computer Arithmetic - Principles, Architecture and Design","author":"hwang","year":"1979","journal-title":"School of Electrical Engineering"},{"key":"ref7","first-page":"505","article-title":"Power Optimization Using Coding Methods on Arithmetic Operators","author":"da costa","year":"2001","journal-title":"Int Symp Signals Circuits and Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1994.471512"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.743408"}],"event":{"name":"15th Symposium on Integrated Circuits and Systems Design","acronym":"SBCCI-02","location":"Porto Alegre, Brazil"},"container-title":["Proceedings. 15th Symposium on Integrated Circuits and Systems Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8229\/25383\/01137631.pdf?arnumber=1137631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T11:27:03Z","timestamp":1489404423000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1137631\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/sbcci.2002.1137631","relation":{},"subject":[]}}