{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T06:09:35Z","timestamp":1768284575816,"version":"3.49.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,6]]},"DOI":"10.1109\/smacd.2016.7520740","type":"proceedings-article","created":{"date-parts":[[2016,8,5]],"date-time":"2016-08-05T17:40:44Z","timestamp":1470418844000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Automated analog IC design constraints generation for a layout-aware sizing approach"],"prefix":"10.1109","author":[{"given":"Andre","family":"Ferreira","sequence":"first","affiliation":[]},{"given":"Nuno","family":"Lourenco","sequence":"additional","affiliation":[]},{"given":"Ricardo","family":"Martins","sequence":"additional","affiliation":[]},{"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2015.7301703"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2013.6673238"},{"key":"ref6","first-page":"1145","article-title":"MARS: Matching-Driven Analog Sizing","volume":"31","author":"eick","year":"2013","journal-title":"IEEE TCAD"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097172"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SMACD.2015.7301697"},{"key":"ref7","article-title":"Floorplan-aware analog IC sizing and optimization based on topological constraints","author":"louren\u00e7o","year":"2014","journal-title":"Integration the VLSI Journal Elsevier"},{"key":"ref2","first-page":"9","article-title":"Analog Circuits Design Using Ant Colony Optimization","volume":"2","author":"gupta","year":"2012","journal-title":"International Journal of Electronics Computer & Communications Technologies"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2143230"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-011-9785-4"}],"event":{"name":"2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","location":"Lisbon, Portugal","start":{"date-parts":[[2016,6,27]]},"end":{"date-parts":[[2016,6,30]]}},"container-title":["2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7513177\/7520642\/07520740.pdf?arnumber=7520740","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T19:26:11Z","timestamp":1475177171000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7520740\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/smacd.2016.7520740","relation":{},"subject":[],"published":{"date-parts":[[2016,6]]}}}