{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T14:31:01Z","timestamp":1730298661811,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,3]]},"DOI":"10.1109\/spl.2010.5483026","type":"proceedings-article","created":{"date-parts":[[2010,12,8]],"date-time":"2010-12-08T17:33:41Z","timestamp":1291829621000},"page":"127-132","source":"Crossref","is-referenced-by-count":0,"title":["Delay modeling for power noise-aware design in Spartan-3A FPGAs"],"prefix":"10.1109","author":[{"given":"Judit F.","family":"Freijedo","sequence":"first","affiliation":[]},{"given":"Maria D.","family":"Valdes","sequence":"additional","affiliation":[]},{"given":"Maria J.","family":"Moure","sequence":"additional","affiliation":[]},{"given":"Lucia","family":"Costas","sequence":"additional","affiliation":[]},{"given":"Juan J.","family":"Rodriguez-Andina","sequence":"additional","affiliation":[]},{"given":"Jorge","family":"Semiao","sequence":"additional","affiliation":[]},{"given":"Fabian","family":"Vargas","sequence":"additional","affiliation":[]},{"given":"Isabel C.","family":"Teixeira","sequence":"additional","affiliation":[]},{"given":"J.","family":"Paulo Teixeira","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2008.191"},{"key":"ref3","article-title":"Design for variability-Design, process, and manufacturing variations in physical design","author":"jilla","year":"2007","journal-title":"White Paper Mentor Graphics"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2008.194"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.146"},{"key":"ref8","first-page":"23","article-title":"An accurate path delay model for multi dynamic testing of digital circuits","author":"freijedo","year":"2008","journal-title":"Proc IEEE Latin American Test Workshop (LATW)"},{"key":"ref7","first-page":"87","article-title":"Using multiple clock schemes and multi test for dynamic fault detection in digital systems","author":"rodriguez-irago","year":"2005","journal-title":"Proc IEEE Latin American Test Workshop (LATW)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2009.5196020"},{"key":"ref9","first-page":"641","article-title":"Time borrowing in high-speed functional units using skew-tolerant domino circuits","volume":"5","author":"jung","year":"2000","journal-title":"Proc IEEE International Symposium on Circuits and Systems (ISCAS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923251"}],"event":{"name":"VI Southern Programmable Logic Conference (SPL)","start":{"date-parts":[[2010,3,24]]},"location":"Ipojuca","end":{"date-parts":[[2010,3,26]]}},"container-title":["2010 VI Southern Programmable Logic Conference (SPL)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5473892\/5482989\/05483026.pdf?arnumber=5483026","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:42:44Z","timestamp":1489887764000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5483026\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,3]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/spl.2010.5483026","relation":{},"subject":[],"published":{"date-parts":[[2010,3]]}}}