{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T09:58:58Z","timestamp":1740131938084,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"European Union's","award":["691178"],"award-info":[{"award-number":["691178"]}]},{"name":"TUBITAK-Career","award":["#113E760"],"award-info":[{"award-number":["#113E760"]}]},{"name":"TUBITAK-NSF","award":["#218E068"],"award-info":[{"award-number":["#218E068"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2020,3,1]]},"DOI":"10.1109\/tc.2019.2950663","type":"journal-article","created":{"date-parts":[[2019,10,31]],"date-time":"2019-10-31T21:12:58Z","timestamp":1572556378000},"page":"427-440","source":"Crossref","is-referenced-by-count":3,"title":["Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices"],"prefix":"10.1109","volume":"69","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6129-9657","authenticated-orcid":false,"given":"Levent","family":"Aksoy","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3103-1809","authenticated-orcid":false,"given":"Mustafa","family":"Altun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"article-title":"Logic synthesis and optimization benchmarks user guide: Version 3.0","year":"1991","author":"yang","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090894"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/s12532-008-0001-1"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.08.004"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.170"},{"year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715123"},{"key":"ref14","first-page":"61","article-title":"Estimation of layout densities for CMOS digital circuits","author":"moraes","year":"1998","journal-title":"Proc Int'l Workshop Power and Timing Modeling Optimization and Simulation"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2661632"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2016.75"},{"key":"ref17","first-page":"1","article-title":"Synthesis of switching lattices of dimensional-reducible boolean functions","author":"bernasconi","year":"2016","journal-title":"Proc Int Conf Very Large Scale Integration"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.05.004"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.08.002"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1084748.1084750"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147093"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/0-387-27705-6"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1126\/science.1066192"},{"key":"ref29","first-page":"399","article-title":"Predicting learnt clauses quality in modern sat solver","author":"audemard","year":"2009","journal-title":"Proc Int Joint Conf Artif Intell"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002303"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3154-4"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.818324"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/nature09749"},{"key":"ref1","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"moore","year":"1965","journal-title":"Electronics"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714809"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.108614"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/800157.805047"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/321386.321387"},{"year":"2016","key":"ref23","article-title":"7 series FPGAs configurable logic block user guide"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009040"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222614"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/12\/8989854\/08889423.pdf?arnumber=8889423","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:09:58Z","timestamp":1651068598000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8889423\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3,1]]},"references-count":32,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tc.2019.2950663","relation":{},"ISSN":["0018-9340","1557-9956","2326-3814"],"issn-type":[{"type":"print","value":"0018-9340"},{"type":"electronic","value":"1557-9956"},{"type":"electronic","value":"2326-3814"}],"subject":[],"published":{"date-parts":[[2020,3,1]]}}}