{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T11:09:15Z","timestamp":1742641755103,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61472159","61572227","61772227"],"award-info":[{"award-number":["61472159","61572227","61772227"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Development Project of Jilin Province of China","award":["20160204022GX","20170101006JC","20170203002GX","20180201045GX","2017C030-1","2017C033"],"award-info":[{"award-number":["20160204022GX","20170101006JC","20170203002GX","20180201045GX","2017C030-1","2017C033"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2020,5]]},"DOI":"10.1109\/tcad.2020.2977074","type":"journal-article","created":{"date-parts":[[2020,2,28]],"date-time":"2020-02-28T22:39:41Z","timestamp":1582929581000},"page":"1031-1044","source":"Crossref","is-referenced-by-count":7,"title":["An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs"],"prefix":"10.1109","volume":"39","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3086-9087","authenticated-orcid":false,"given":"Dalin","family":"Li","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3233-3777","authenticated-orcid":false,"given":"Lan","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Teng","family":"Gao","sequence":"additional","affiliation":[]},{"given":"Yang","family":"Feng","sequence":"additional","affiliation":[]},{"given":"Adriano","family":"Tavares","sequence":"additional","affiliation":[]},{"given":"Kangping","family":"Wang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Arm Developer","year":"2018","key":"ref33"},{"journal-title":"Vivado Design Suite","year":"2012","key":"ref32"},{"journal-title":"Zynq-7000 SoC Packaging and Pinout Product Specification UG865 (v1 8 1)","year":"2018","key":"ref31"},{"journal-title":"UltraScale and UltraScale + FPGAs Packaging and Pinouts Product Specification UG575 (v1 12)","year":"2019","key":"ref30"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1155\/2016\/4246596"},{"journal-title":"AXI Memory Mapped to PCI Express (PCIe) Gen2 v2 8 LogiCORE IP Product Guide","year":"2018","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/71.224219"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950427"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/359619.359631"},{"key":"ref13","first-page":"29","article-title":"Sorting networks on FPGA","author":"prasad","year":"2011","journal-title":"Proc Int Conf WSEAS Int Conf Telecommun Informat Microelectron Nanoelectron Optoelectron"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-011-0232-z"},{"key":"ref15","first-page":"217","article-title":"Design of a pipelined and expandable sorting architecture with simple control scheme","author":"lin","year":"2002","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1007\/BF02107058","article-title":"A shift register architecture for high-speed data sorting","volume":"11","author":"chen","year":"1995","journal-title":"J VLSI Signal Process Syst Signal Image Video Technol"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-09661-2_2"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.14"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/963539"},{"journal-title":"Relational Mathematics","year":"2011","author":"schmidt","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.14778\/1687627.1687730"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4612-0053-6"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1132960.1132964"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1327452.1327492"},{"key":"ref29","first-page":"600","article-title":"Partially ordered sets","volume":"63","author":"dan","year":"2008","journal-title":"Amer J Math"},{"journal-title":"A block-sorting lossless data compression algorithm","year":"1994","author":"burrows","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1111\/j.1467-8659.2009.01377.x"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ROBOT.1996.506947"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/17.4.324"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2015.40"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00067"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00067"},{"journal-title":"Vivado Design Suite User Guide High-Level Synthesis UG902","year":"2018","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847268"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2821561"},{"journal-title":"Parallel Programming for FPGAs","year":"2018","author":"kastner","key":"ref25"}],"container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/43\/9075140\/09018097.pdf?arnumber=9018097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:07:08Z","timestamp":1651068428000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9018097\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5]]},"references-count":35,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tcad.2020.2977074","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"type":"print","value":"0278-0070"},{"type":"electronic","value":"1937-4151"}],"subject":[],"published":{"date-parts":[[2020,5]]}}}