{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,5]],"date-time":"2024-07-05T21:21:07Z","timestamp":1720214467506},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2008,11,1]],"date-time":"2008-11-01T00:00:00Z","timestamp":1225497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/tvlsi.2008.2001141","type":"journal-article","created":{"date-parts":[[2008,10,22]],"date-time":"2008-10-22T18:56:47Z","timestamp":1224701807000},"page":"1545-1558","source":"Crossref","is-referenced-by-count":7,"title":["Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution"],"prefix":"10.1109","volume":"16","author":[{"given":"Manuel G.","family":"Gericota","sequence":"first","affiliation":[]},{"given":"Gustavo R.","family":"Alves","sequence":"additional","affiliation":[]},{"given":"Miguel L.","family":"Silva","sequence":"additional","affiliation":[]},{"given":"Jos\u00c9 M.","family":"Ferreira","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"70","article-title":"relocation and defragmentation for heterogeneous reconfigurable systems","author":"koester","year":"2006","journal-title":"Proc Int Conf Eng Reconfig Syst Algorithms"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/s11334-005-0003-3"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/11802839_34"},{"key":"ref32","first-page":"72","article-title":"programmable logic devices: a test approach for the input\/output blocks and pad-to-pin interconnections","author":"gericota","year":"2003","journal-title":"4th IEEE Latin-Amer Test Workshop Dig Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360344"},{"key":"ref37","first-page":"196","article-title":"area reclamation strategies and metrics for sram-based reconfigurable devices","author":"ejnioui","year":"2005","journal-title":"Proc Int Conf Eng Reconfig Syst Algorithms"},{"key":"ref36","first-page":"1097","article-title":"compile-time optimization of dynamic hardware reconfigurations","author":"teich","year":"1999","journal-title":"Proc Int Conf Parallel Distrib Process Techn Appl"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20000485"},{"key":"ref34","first-page":"124","article-title":"dynasty: a temporal floorplanning based cad framework for dynamically reconfigurable logic systems","author":"vasilko","year":"1999","journal-title":"Proc 9th Int Workshop Field-Program Logic Appl"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/12.656073"},{"key":"ref40","first-page":"1","article-title":"jbits java based interface for reconfigurable computing","author":"guccione","year":"1999","journal-title":"Proc 2nd Military Aerosp Appl Program Devices Technol Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/92.678870"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805830"},{"key":"ref13","first-page":"960","article-title":"An efficient algorithm for finding empty space for online FPGA placement","author":"handa","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510883"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639662"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743180"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.1999.804522"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/92.678888"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/12.822563"},{"key":"ref28","year":"1999","journal-title":"ITC 99 Benchmarks"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998354"},{"key":"ref27","first-page":"302","article-title":"on-line defragmentation for run-time partially reconfigurable fpgas","author":"gericota","year":"2002","journal-title":"Proc Int Conf Field Program Logic and Appl"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.920831"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/92.736139"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/1-4020-3128-9_10"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303107"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268908"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.821411"},{"key":"ref2","first-page":"485","article-title":"an enhanced static-list scheduling algorithm for temporal partitioning onto rpus","author":"cardoso","year":"1999","journal-title":"Proc Int Conf VLSI Des"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860742"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279481"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/54.655181"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/54.655182"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655840"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TSSC.1968.300136"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639653"},{"key":"ref41","year":"0","journal-title":"?Xilinx ISE tools ?"},{"key":"ref23","year":"2001","journal-title":"IEEE standard test access port and boundary scan architecture"},{"key":"ref26","first-page":"165","article-title":"active replication: towards a truly sram-based fpga on-line concurrent testing","author":"gericota","year":"2002","journal-title":"Proc 8th IEEE On-Line Testing Workshop"},{"key":"ref25","first-page":"330","article-title":"test generation optimization for a fpga application-oriented test procedure","author":"renovell","year":"2000","journal-title":"Proc 15th Des Circuits Integr Syst Conf"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/4655424\/04655626.pdf?arnumber=4655626","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:07Z","timestamp":1638219367000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4655626\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":42,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2008.2001141","relation":{},"ISSN":["1063-8210"],"issn-type":[{"value":"1063-8210","type":"print"}],"subject":[],"published":{"date-parts":[[2008,11]]}}}