{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,6]],"date-time":"2026-05-06T16:10:57Z","timestamp":1778083857219,"version":"3.51.4"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/tvlsi.2013.2242501","type":"journal-article","created":{"date-parts":[[2013,2,14]],"date-time":"2013-02-14T19:04:37Z","timestamp":1360868677000},"page":"372-383","source":"Crossref","is-referenced-by-count":57,"title":["Split-SAR ADCs: Improved Linearity With Power and Speed Optimization"],"prefix":"10.1109","volume":"22","author":[{"given":"Yan","family":"Zhu","sequence":"first","affiliation":[]},{"given":"Chi-Hang","family":"Chan","sequence":"additional","affiliation":[]},{"given":"U-Fat","family":"Chio","sequence":"additional","affiliation":[]},{"given":"Sai-Weng","family":"Sin","sequence":"additional","affiliation":[]},{"given":"Seng-Pan","family":"U","sequence":"additional","affiliation":[]},{"given":"Rui Paulo","family":"Martins","sequence":"additional","affiliation":[]},{"given":"Franco","family":"Maloberti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","year":"2012","journal-title":"Datasheet of Low Dropout Linear Regulator"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1328168"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2050937"},{"key":"ref12","first-page":"642","article-title":"A power-efficient capacitor structure for high-speed charge recycling SAR ADCs","author":"zhu","year":"2008","journal-title":"Proc IEEE Int Conf Electron Circuits Syst"},{"key":"ref13","first-page":"542","article-title":"A 32 mW 1.25 GS\/s 6 b 2 b\/step SAR ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"cao","year":"2008","journal-title":"Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2107214"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2048387"},{"key":"ref16","first-page":"574","article-title":"A 6 b 600 MS\/s 5.3-mW asynchronous ADC in 0.13-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS","author":"chen","year":"2006","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref17","first-page":"145","article-title":"A 9 b 100 MS\/s 1.46 mW SAR ADC in 65 nm CMOS","author":"chen","year":"2009","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref18","first-page":"246","article-title":"A 9.4-ENOB 1 V 3.8 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm W}$<\/tex><\/formula> 100 kS\/s SAR ADC with time-domain comparator","author":"agnes","year":"2008","journal-title":"Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280859"},{"key":"ref28","author":"gustavsson","year":"2000","journal-title":"CMOS Data Converters for Communications"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433967"},{"key":"ref27","first-page":"176","article-title":"A 1.2-V 10-b 20-Msample\/s nonbinary successive approximation ADC in 0.13-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex> <\/formula> CMOS","author":"kuttner","year":"2002","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref3","first-page":"236","article-title":"A 0.92 mW 10-bit 50-MS\/s SAR ADC in 0.13 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS process","author":"liu","year":"2009","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891718"},{"key":"ref29","first-page":"922","article-title":"Linearity analysis on a series-split capacitor array for high-speed SAR ADCs","author":"zhu","year":"2008","journal-title":"Proc IEEE Midwest Symp Circuits Syst"},{"key":"ref5","first-page":"250","article-title":"A 1.2 V 4.5 mW 10 b 100 MS\/s pipeline ADC","author":"boulemnakher","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref8","first-page":"164","article-title":"A 50 MS\/s 9.9 mW pipeline ADC with 58 dB SNDR in 0.18 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS using capacitive charge-pumps","author":"ahmed","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2052376"},{"key":"ref2","first-page":"238","article-title":"An 820 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm W}$<\/tex><\/formula> 9 b 40 MS\/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS","author":"giannini","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4586012"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373386"},{"key":"ref20","first-page":"384","article-title":"10 b 50 MS\/s 820 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm W}$<\/tex><\/formula> SAR ADC with on-chip digital calibration","author":"yoshioka","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref22","first-page":"333","article-title":"Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs","author":"wong","year":"2009","journal-title":"IEEE Int Conf on SOC Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537634"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892169"},{"key":"ref26","first-page":"1164","article-title":"A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs","author":"chio","year":"2008","journal-title":"Proc IEEE Asia Pacific Conf Circuits Syst"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464555"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6716075\/06462023.pdf?arnumber=6462023","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:31:42Z","timestamp":1642005102000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6462023\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":30,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2242501","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,2]]}}}