{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:37Z","timestamp":1740133297138,"version":"3.37.3"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2017,1,1]],"date-time":"2017-01-01T00:00:00Z","timestamp":1483228800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001871","name":"European Regional Development Fund within the Operational Programme for Competitiveness and Internationalisation\u2013COMPETE 2020 Programme through the Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["POCI-01-0145-FEDER-006961"],"award-info":[{"award-number":["POCI-01-0145-FEDER-006961"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Funds through the Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","award":["UID\/EEA\/50014\/2013"],"award-info":[{"award-number":["UID\/EEA\/50014\/2013"]}]},{"DOI":"10.13039\/501100001871","name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","doi-asserted-by":"publisher","award":["SFRH\/BD\/80225\/2011"],"award-info":[{"award-number":["SFRH\/BD\/80225\/2011"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2017,1]]},"DOI":"10.1109\/tvlsi.2016.2573640","type":"journal-article","created":{"date-parts":[[2016,7,7]],"date-time":"2016-07-07T20:15:53Z","timestamp":1467922553000},"page":"21-34","source":"Crossref","is-referenced-by-count":6,"title":["Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces"],"prefix":"10.1109","volume":"25","author":[{"given":"Nuno M. C.","family":"Paulino","sequence":"first","affiliation":[]},{"given":"Joao Canas","family":"Ferreira","sequence":"additional","affiliation":[]},{"given":"Joao M. P.","family":"Cardoso","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.61"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1122"},{"key":"ref13","first-page":"12","article-title":"Design of a pipelined and parameterized VLIW processor: $\\rho $ -VEX v2","author":"seedorf","year":"2012","journal-title":"Proc HiPEAC Workshop on Reconfigurable Computing"},{"journal-title":"Megablock Extractor for MicroBlaze v0 7 14","year":"2015","author":"bispo","key":"ref14"},{"journal-title":"Livermore Loops Coded in C","year":"1992","author":"peters","key":"ref15"},{"journal-title":"TMS320C6000 Image Library (IMGLIB)—SPRC264","year":"2008","key":"ref16"},{"journal-title":"7 Series FPGAs Overview (v1 17)","year":"2015","key":"ref17"},{"journal-title":"Fusion Digital Power Designer","year":"2016","key":"ref18"},{"journal-title":"Embedded Computing A VLIW Approach to Architecture Compilers and Tools","year":"2005","author":"fisher","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2209886"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555314"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2014.6893197"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1509288.1509294"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1155\/2013\/340316"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2012.2235844"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2656106.2656125"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1145\/2629468","article-title":"A reconfigurable architecture for binary acceleration of loops with memory accesses","volume":"7","author":"paulino","year":"2015","journal-title":"ACM Trans Reconfigurable Technol Syst"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-8588-8","author":"coussy","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.9"},{"key":"ref22","first-page":"1208","article-title":"Transparent reconfigurable acceleration for heterogeneous embedded applications","author":"beck","year":"2008","journal-title":"Proc Design Autom Test Eur"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-010-0505-0"},{"key":"ref24","first-page":"276","article-title":"Increasing hardware efficiency with multifunction loop accelerators","author":"mahlke","year":"2006","journal-title":"Proc Int Conf Hardw \/Softw Codesign Syst Synthesis (CODES-ISSS)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.03.005"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2014.29"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/7797597\/07506263.pdf?arnumber=7506263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:12:15Z","timestamp":1642003935000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7506263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,1]]},"references-count":25,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2016.2573640","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2017,1]]}}}