{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T04:44:50Z","timestamp":1768193090408,"version":"3.49.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,1,1]],"date-time":"2019-01-01T00:00:00Z","timestamp":1546300800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Instituto de Telecomunica\u00e7\u00f5es","award":["RAPID UID\/EEA\/50008\/2013"],"award-info":[{"award-number":["RAPID UID\/EEA\/50008\/2013"]}]},{"name":"Funda\u00e7\u00f5o para a Ci\u00eancia e Tecnologia","award":["SFRH\/BPD\/104648\/2014"],"award-info":[{"award-number":["SFRH\/BPD\/104648\/2014"]}]},{"name":"Funda\u00e7\u00f5o para a Ci\u00eancia e Tecnologia","award":["SFRH\/BPD\/120009\/2016"],"award-info":[{"award-number":["SFRH\/BPD\/120009\/2016"]}]},{"name":"Macao Science and Technology Development Fund and SKL Fund"},{"DOI":"10.13039\/501100004733","name":"University of Macau","doi-asserted-by":"crossref","award":["MYRG-2017-00185"],"award-info":[{"award-number":["MYRG-2017-00185"]}],"id":[{"id":"10.13039\/501100004733","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1109\/tvlsi.2018.2872410","type":"journal-article","created":{"date-parts":[[2018,10,10]],"date-time":"2018-10-10T18:58:18Z","timestamp":1539197898000},"page":"69-82","source":"Crossref","is-referenced-by-count":27,"title":["Many-Objective Sizing Optimization of a Class-C\/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8251-1415","authenticated-orcid":false,"given":"Ricardo","family":"Martins","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9625-6435","authenticated-orcid":false,"given":"Nuno","family":"Lourenco","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1687-1447","authenticated-orcid":false,"given":"Nuno","family":"Horta","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4195-4551","authenticated-orcid":false,"given":"Jun","family":"Yin","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3579-8740","authenticated-orcid":false,"given":"Pui-In","family":"Mak","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","author":"hegazi","year":"2005","journal-title":"The Designer's Guide to High-Purity Oscillators"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889371"},{"key":"ref11","article-title":"Automated design of analog and high-frequency circuits","author":"liu","year":"2014","journal-title":"Studies in Computational Intelligence"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.924852"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810623"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.802267"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002046"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865123"},{"key":"ref17","article-title":"Synthesis of LC-oscillators using rival multi-objective multi-constraint optimization kernels","author":"p\u00f3voa","year":"2014","journal-title":"Performance Optimization Techniques in Analog Mixed-Signal and Radio-Frequency Circuit Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2015.04.005"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482437"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2602214"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2271531"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642207"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-00098-5"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842851"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310340"},{"key":"ref8","first-page":"374","article-title":"A multiband 40 nm CMOS LTE SAW-less modulator with ?60 dBc C-IM3","author":"giannini","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"348","article-title":"A power-scalable DCO for multi-standard GSM\/WCDMA frequency synthesizers","volume":"49","author":"liscidini","year":"2012","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2273823"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.658619"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004867"},{"key":"ref20","year":"2018","journal-title":"Cadence"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2564362"},{"key":"ref21","year":"2018","journal-title":"MunEDA"},{"key":"ref24","article-title":"Two-step RF IC block synthesis with pre-optimized inductors and full layout generation in-the-loop","author":"martins","year":"0","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.02.005"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2016.04.009"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2014.07.002"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8595476\/08488500.pdf?arnumber=8488500","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:53:55Z","timestamp":1657745635000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8488500\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,1]]},"references-count":30,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2872410","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,1]]}}}