{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T05:10:01Z","timestamp":1747977001737,"version":"3.41.0"},"reference-count":69,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tvlsi.2025.3544860","type":"journal-article","created":{"date-parts":[[2025,3,21]],"date-time":"2025-03-21T19:36:07Z","timestamp":1742585767000},"page":"1751-1764","source":"Crossref","is-referenced-by-count":0,"title":["<i>ResiLogic<\/i>: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7235-9691","authenticated-orcid":false,"given":"Ahmad T.","family":"Sheikh","sequence":"first","affiliation":[{"name":"CEMSE Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4898-9394","authenticated-orcid":false,"given":"Ali","family":"Shoker","sequence":"additional","affiliation":[{"name":"CEMSE Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0568-5048","authenticated-orcid":false,"given":"Suhaib A.","family":"Fahmy","sequence":"additional","affiliation":[{"name":"CEMSE Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"}]},{"given":"Paulo","family":"Esteves-Verissimo","sequence":"additional","affiliation":[{"name":"CEMSE Division, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2005.862424"},{"article-title":"A comprehensive survey on non-invasive fault injection attacks","year":"2023","author":"Shuvo","key":"ref2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-30596-3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45177-3_1"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126618500974"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1992.224350"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250119"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3156799"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RADECS.2013.6937382"},{"volume-title":"Chips for America Act & Fabs Act","year":"2023","key":"ref10"},{"volume-title":"European Chips Act: The Chips for Europe Initiative","year":"2023","key":"ref11"},{"volume-title":"How and When the Chip Shortage Will End, in 4 Charts","year":"2023","key":"ref12"},{"article-title":"Openroad: Toward a self-driving, open-source digital layout implementation tool chain","volume-title":"Proc. Government Microcircuit Appl. Crit. Technol. Conf.","author":"Ajayi","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-444-53114-8.00002-9"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2022.3169641"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1388969.1389075"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3434304"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2000.876036"},{"key":"ref19","first-page":"23","article-title":"The methodology of n-version programming","volume":"3","author":"Avizienis","year":"1995","journal-title":"Softw. Fault Tolerance"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1002\/spe.2180"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1201\/9781315275567"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.032271057"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2010.5550343"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2231707"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3603619"},{"volume-title":"Rt Polarfire\u00ae: TMR and Spatial Separation for Higher Reliability","year":"2023","key":"ref26"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2011.9"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0022-y"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-62609-9_6"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-26896-0_8"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1063\/1.2965810"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS50870.2020.9159733"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2008.4505310"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593144"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-68511-3"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.224020"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53140-2_7"},{"key":"ref40","doi-asserted-by":"crossref","DOI":"10.1201\/b13609","volume-title":"Security in Sensor Networks","author":"Xiao","year":"2016"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3073946"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00043"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2943570"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391606"},{"key":"ref45","first-page":"256","article-title":"Systolic arrays (for VLSI)","volume":"1","author":"Kung","year":"1979","journal-title":"Sparse Matrix Proceedings 1978"},{"article-title":"The systematic design of systolic arrays","year":"1983","author":"Quinton","key":"ref46"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/3604802"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ICECCE49384.2020.9179433"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1017\/ATSIP.2017.9"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.50"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1002\/sea2.12136"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ISED.2017.8303943"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH54963.2022.00016"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3410154"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH61463.2024.00014"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM53951.2022.9786123"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3656246"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/43.536711"},{"key":"ref60","first-page":"1","article-title":"Yosys-a free verilog synthesis suite","volume-title":"Proc. 21st Austrian Workshop Microelectron (Austrochip)","volume":"97","author":"Wolf"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"article-title":"Logic synthesis and optimization benchmarks","year":"1988","author":"Lisanke","key":"ref62"},{"article-title":"Logic synthesis and optimization benchmarks","year":"1991","author":"Yang","key":"ref63"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-68071-8_9"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.95"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2569532"},{"key":"ref69","first-page":"4","article-title":"Sis: A system for sequential circuit synthesis","volume":"94720","author":"Singh","year":"1992"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11010805\/10934979.pdf?arnumber=10934979","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T04:28:21Z","timestamp":1747974501000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10934979\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":69,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3544860","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}