{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,21]],"date-time":"2026-08-21T18:40:10Z","timestamp":1787337610330,"version":"3.56.0"},"reference-count":37,"publisher":"Society for Industrial & Applied Mathematics (SIAM)","issue":"6","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["SIAM J. Comput."],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>We describe an algorithm that finds a minimum cost schedule, including spill code, for a register-constrained machine that can issue up to one arithmetic operation and one memory access operation at a time, under the restrictions that the dependence graph is a full binary tree, all arithmetic and store operations have unit latency, and all load operations have a latency of 1 or all load operations have a latency of 2. This problem is a generalization of two problems whose efficient solutions are well understood: optimaldual-issue scheduling without spills for binary expression trees, solved by Bernstein, Jaffe, and Rodeh [SIAM J. Comput., 18 (1989), pp. 1098--1127], and optimal single-issue scheduling with spill code and delayed loads, solved by Kurlander, Proebsting, and Fischer [ ACM Transactions on Programming Languages and Systems, 17 (1995), pp. 740--776], both assuming a fixed number of registers. We show that the algorithm's complexity is O(nk) where n is the number of operations to be scheduled and k is the number of spills in the schedule. The cost of a \"contiguous\" schedule (i.e., its length) is shown to be $\\rho + 2k + g + |A|$, where $\\rho$ is the number of registers used, |A| is the number of arithmetic operations, k is the number of spills, and g is the number of empty slots in the associated single processor schedule. Therefore all contiguous schedules formed from optimal single processor schedules have minimum cost.<\/jats:p>","DOI":"10.1137\/s009753979834610x","type":"journal-article","created":{"date-parts":[[2003,6,11]],"date-time":"2003-06-11T11:12:06Z","timestamp":1055329926000},"page":"1921-1941","source":"Crossref","is-referenced-by-count":4,"title":["Dual-Issue Scheduling for Binary Trees with Spills and Pipelined Loads"],"prefix":"10.1137","volume":"30","author":[{"given":"Waleed M.","family":"Meleis","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"351","published-online":{"date-parts":[[2006,7,27]]},"reference":[{"key":"R1","doi-asserted-by":"publisher","DOI":"10.1145\/321958.321970"},{"key":"R2","doi-asserted-by":"crossref","unstructured":"P. Bergner, P. Dahl, D. Engebretsen, and M. O\u2019Keefe,\n                      Spill code minimization via interference region spilling\n                      , in ACM SIGPLAN Conference on Programming Language Design and Implementation, Las Vegas, NV, ACM Press, 1997.","DOI":"10.1145\/258915.258941"},{"key":"R3","doi-asserted-by":"publisher","DOI":"10.1145\/59287.59291"},{"key":"R4","doi-asserted-by":"publisher","DOI":"10.1137\/0218074"},{"key":"R5","doi-asserted-by":"publisher","DOI":"10.1109\/12.29469"},{"key":"R6","unstructured":"P. Bose,\n                      Optimal code generation for expressions in super scalar machines\n                      , in Proceedings of the Fall Joint Computer Conference, IEEE Computer Society Press, Los Alamitos, CA, 1986, pp. 372\u2013379."},{"key":"R7","doi-asserted-by":"crossref","unstructured":"D. Bradlee, S. Eggers, and R. Henry,\n                      Integrating register allocation and instruction scheduling for RISCS\n                      , in Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, ACM Press, 1991.","DOI":"10.1145\/106972.106986"},{"key":"R8","doi-asserted-by":"publisher","DOI":"10.1145\/74818.74843"},{"key":"R9","doi-asserted-by":"publisher","DOI":"10.1145\/177492.177575"},{"key":"R10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1980.1675569"},{"key":"R11","doi-asserted-by":"publisher","DOI":"10.1145\/321958.321971"},{"key":"R12","doi-asserted-by":"crossref","unstructured":"D. Callahan and B. Koblenz,\n                      Register allocation via hierarchical graph coloring\n                      , in ACM SIGPLAN \u201991 Conference on Programming Language Design and Implementation, Toronto, Canada, ACM Press, 1991.","DOI":"10.1145\/113445.113462"},{"key":"R13","doi-asserted-by":"publisher","DOI":"10.1006\/jagm.2000.1095"},{"key":"R14","doi-asserted-by":"publisher","DOI":"10.1145\/88616.88621"},{"key":"R15","doi-asserted-by":"publisher","DOI":"10.1007\/BF00288685"},{"key":"R16","volume-title":"Introduction to algorithms","author":"Manber Udi","year":"1989"},{"key":"R17","doi-asserted-by":"publisher","DOI":"10.1016\/0096-0551(81)90048-5"},{"key":"R18","doi-asserted-by":"crossref","unstructured":"G. J. Chaitin, et al.\n                      Register allocation and spilling via graph coloring\n                      , in Proceedings of the ACM SIGPLAN \u201986 Symposium on Compiler Construction, New York, 1982, pp. 98\u2013105.","DOI":"10.1145\/800230.806984"},{"key":"R19","doi-asserted-by":"publisher","DOI":"10.1006\/jagm.2000.1095"},{"key":"R20","doi-asserted-by":"publisher","DOI":"10.1145\/229542.229546"},{"key":"R21","doi-asserted-by":"crossref","unstructured":"P. B. Gibbons and S. S. Muchnick,\n                      Efficient instruction scheduling for a pipelined architecture\n                      , in Proceedings of the ACM SIGPLAN \u201986 Symposium on Compiler Construction, New York, 1986, pp. 11\u201316.","DOI":"10.1145\/12276.13312"},{"key":"R22","doi-asserted-by":"crossref","unstructured":"J. R. Goodman and W. C. Hsu,\n                      Code scheduling and register allocation in large basic blocks\n                      , in Proceedings of the 1988 International Conference on Supercomputing, Orlando, FL, ACM Press, 1988, pp. 442\u2013452.","DOI":"10.1145\/55364.55407"},{"key":"R23","doi-asserted-by":"crossref","unstructured":"J. Hennessy and T. Gross,\n                      Code generation and reorganization in the presence of pipeline constraints\n                      , in 9th Annual ACM Symposium on Principles of Programming Languages, Albuquerque, NM, ACM Press, 1982, pp. 120\u2013127.","DOI":"10.1145\/582153.582166"},{"key":"R24","doi-asserted-by":"publisher","DOI":"10.1145\/2166.357217"},{"key":"R25","doi-asserted-by":"publisher","DOI":"10.1145\/321312.321317"},{"key":"R26","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1989.559775"},{"key":"R27","doi-asserted-by":"publisher","DOI":"10.1287\/opre.9.6.841"},{"key":"R28","doi-asserted-by":"publisher","DOI":"10.1145\/213978.213987"},{"key":"R29","doi-asserted-by":"crossref","unstructured":"G. Lueh and T. Gross,\n                      Call\u2010cost directed register allocation\n                      , in ACM SIGPLAN Conference on Programming Language Design and Implementation, Las Vegas, NV, ACM Press, 1997.","DOI":"10.1145\/258915.258942"},{"key":"R30","doi-asserted-by":"publisher","DOI":"10.1145\/363534.363549"},{"key":"R31","doi-asserted-by":"publisher","DOI":"10.1145\/155183.155190"},{"key":"R32","doi-asserted-by":"publisher","DOI":"10.1145\/173262.155114"},{"key":"R33","doi-asserted-by":"publisher","DOI":"10.1145\/236114.236117"},{"key":"R34","doi-asserted-by":"publisher","DOI":"10.1145\/362848.362859"},{"key":"R35","doi-asserted-by":"publisher","DOI":"10.1137\/0204020"},{"key":"R36","doi-asserted-by":"publisher","DOI":"10.1145\/321607.321620"},{"key":"R37","doi-asserted-by":"publisher","DOI":"10.1016\/S0022-0000(75)80008-0"}],"container-title":["SIAM Journal on Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/epubs.siam.org\/doi\/pdf\/10.1137\/S009753979834610X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,8,21]],"date-time":"2026-08-21T18:20:14Z","timestamp":1787336414000},"score":1,"resource":{"primary":{"URL":"https:\/\/epubs.siam.org\/doi\/10.1137\/S009753979834610X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,1]]},"references-count":37,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1137\/S009753979834610X"],"URL":"https:\/\/doi.org\/10.1137\/s009753979834610x","relation":{},"ISSN":["0097-5397","1095-7111"],"issn-type":[{"value":"0097-5397","type":"print"},{"value":"1095-7111","type":"electronic"}],"subject":[],"published":{"date-parts":[[2001,1]]}}}