{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T05:47:27Z","timestamp":1744436847759},"reference-count":6,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int. J. Neur. Syst."],"published-print":{"date-parts":[[2000,6]]},"abstract":"<jats:p> We propose a semi-automatic HW\/SW codesign flow for low-power and low-cost Neuro-Fuzzy embedded systems. Applications range from fast prototyping of embedded systems to high-speed simulation of Simulink models and rapid design of Neuro-Fuzzy devices. The proposed codesign flow works with different technologies and architectures (namely, software, digital and analog). We have used The Mathworks' Simulink\u00a9 environment for functional specification and for analysis of performance criteria such as timing (latency and throughput), power dissipation, size and cost. The proposed flow can exploit trade-offs between SW and HW as well as between digital and analog implementations, and it can generate, respectively, the C, VHDL and SKILL codes of the selected architectures. <\/jats:p>","DOI":"10.1142\/s0129065700000193","type":"journal-article","created":{"date-parts":[[2003,4,22]],"date-time":"2003-04-22T07:45:54Z","timestamp":1050997554000},"page":"211-226","source":"Crossref","is-referenced-by-count":5,"title":["SIMULINK-BASED HW\/SW CODESIGN OF EMBEDDED NEURO-FUZZY SYSTEMS"],"prefix":"10.1142","volume":"10","author":[{"given":"L. M.","family":"Reyneri","sequence":"first","affiliation":[{"name":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy"}]},{"given":"M.","family":"Chiaberge","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy"}]},{"given":"L.","family":"Lavagno","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Politecnico di Torino, C.so Duca  degli Abruzzi, 24, 10129 Torino, Italy"}]},{"given":"B.","family":"Pino","sequence":"additional","affiliation":[{"name":"Dep.to de Arquitectura y Tecnologia de Computadores, Univ. de Granada, Campus Universitario de Fuentenueva, Granada, Spain"}]},{"given":"E.","family":"Miranda","sequence":"additional","affiliation":[{"name":"Mechatronics Lab, Politecnico di Torino, C.so Duca degli Abruzzi,  24, 10129 Torino, Italy"}]}],"member":"219","published-online":{"date-parts":[[2012,4,19]]},"reference":[{"key":"p_2","doi-asserted-by":"publisher","DOI":"10.1109\/72.774224"},{"key":"p_4","doi-asserted-by":"publisher","DOI":"10.1109\/5.558710"},{"key":"p_8","doi-asserted-by":"publisher","DOI":"10.1049\/el:19961272"},{"key":"p_9","first-page":"40","author":"Reyneri L.M.","year":"1995","journal-title":"IEEE MICRO"},{"key":"p_10","doi-asserted-by":"publisher","DOI":"10.1109\/81.477205"},{"key":"p_15","doi-asserted-by":"publisher","DOI":"10.1109\/92.335012"}],"container-title":["International Journal of Neural Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129065700000193","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T17:06:53Z","timestamp":1565111213000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129065700000193"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,6]]},"references-count":6,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2012,4,19]]},"published-print":{"date-parts":[[2000,6]]}},"alternative-id":["10.1142\/S0129065700000193"],"URL":"https:\/\/doi.org\/10.1142\/s0129065700000193","relation":{},"ISSN":["0129-0657","1793-6462"],"issn-type":[{"value":"0129-0657","type":"print"},{"value":"1793-6462","type":"electronic"}],"subject":[],"published":{"date-parts":[[2000,6]]}}}