{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T16:19:23Z","timestamp":1649002763554},"reference-count":10,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[2002,3]]},"abstract":"<jats:p> The tree interconnection network lends itself to several suitably structured applications. However, the low connectivity at each node, traffic congestion and single point of failure at the root node reduce reliability and availability. Both the hypertree and X-tree are fault-tolerant variants of the basic tree network and have been the focus of more recent implementation and research interest. In this paper, we consider a recently proposed family of interconnection networks known as the Josephus Cubes and show how hypertrees, X-trees and ringed X-trees of arbitrary height can be near-optimally embedded in this novel interconnection network. <\/jats:p>","DOI":"10.1142\/s012962640200077x","type":"journal-article","created":{"date-parts":[[2012,9,1]],"date-time":"2012-09-01T13:07:47Z","timestamp":1346504867000},"page":"3-16","source":"Crossref","is-referenced-by-count":0,"title":["EMBEDDING OF FAULT-TOLERANT TREES IN THE JOSEPHUS CUBE"],"prefix":"10.1142","volume":"12","author":[{"given":"PETER K. K.","family":"LOH","sequence":"first","affiliation":[{"name":"School of Computer Engineering, Nanyang Technological  University, Blk N4, #2A-32, Nanyang Avenue, Singapore 639798, Singapore"}]},{"given":"W. J.","family":"HSU","sequence":"additional","affiliation":[{"name":"School of Computer Engineering, Nanyang Technological  University, Blk N4, #2A-32, Nanyang Avenue, Singapore 639798, Singapore"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"p_1","doi-asserted-by":"publisher","DOI":"10.1142\/S012962649200026X"},{"key":"p_3","first-page":"30","author":"Goodman J.R.","journal-title":"IEEE Transactions on Computers"},{"key":"p_5","doi-asserted-by":"publisher","DOI":"10.1093\/comjnl\/39.1.45"},{"key":"p_7","doi-asserted-by":"publisher","DOI":"10.1109\/24.126670"},{"key":"p_8","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(88)90019-3"},{"key":"p_9","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1993.1108"},{"key":"p_13","doi-asserted-by":"publisher","DOI":"10.1109\/71.205649"},{"key":"p_14","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1995.1045"},{"key":"p_15","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-8191(99)00111-8"},{"key":"p_16","doi-asserted-by":"publisher","DOI":"10.1109\/12.376173"}],"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S012962640200077X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T16:19:44Z","timestamp":1565108384000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S012962640200077X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,3]]},"references-count":10,"journal-issue":{"issue":"01","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2002,3]]}},"alternative-id":["10.1142\/S012962640200077X"],"URL":"https:\/\/doi.org\/10.1142\/s012962640200077x","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2002,3]]}}}