{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T10:22:14Z","timestamp":1779358934920,"version":"3.51.4"},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[2011,6]]},"abstract":"<jats:p> In this paper, we present OmpSs, a programming model based on OpenMP and StarSs, that can also incorporate the use of OpenCL or CUDA kernels. We evaluate the proposal on different architectures, SMP, GPUs, and hybrid SMP\/GPU environments, showing the wide usefulness of the approach. The evaluation is done with six different benchmarks, Matrix Multiply, BlackScholes, Perlin Noise, Julia Set, PBPI and FixedGrid. We compare the results obtained with the execution of the same benchmarks written in OpenCL or OpenMP, on the same architectures. The results show that OmpSs greatly outperforms both environments. With the use of OmpSs the programming environment is more flexible than traditional approaches to exploit multiple accelerators, and due to the simplicity of the annotations, it increases programmer's productivity. <\/jats:p>","DOI":"10.1142\/s0129626411000151","type":"journal-article","created":{"date-parts":[[2011,6,23]],"date-time":"2011-06-23T07:25:37Z","timestamp":1308813937000},"page":"173-193","source":"Crossref","is-referenced-by-count":467,"title":["OmpSs: A PROPOSAL FOR PROGRAMMING HETEROGENEOUS MULTI-CORE ARCHITECTURES"],"prefix":"10.1142","volume":"21","author":[{"given":"ALEJANDRO","family":"DURAN","sequence":"first","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"EDUARD","family":"AYGUAD\u00c9","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"},{"name":"Computer Architecture Departament, Univ. Polit\u00e8cnica de Catalunya, C. Jordi Girona 1\u20133, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"ROSA M.","family":"BADIA","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"},{"name":"IIIA - Artificial Intelligence Research Institute, CSIC - Spanish National Research Council, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"JES\u00daS","family":"LABARTA","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"},{"name":"Computer Architecture Departament, Univ. Polit\u00e8cnica de Catalunya, C. Jordi Girona 1\u20133, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"LUIS","family":"MARTINELL","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"XAVIER","family":"MARTORELL","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"},{"name":"Computer Architecture Departament, Univ. Polit\u00e8cnica de Catalunya, C. Jordi Girona 1\u20133, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"JUDIT","family":"PLANAS","sequence":"additional","affiliation":[{"name":"Computer Sciences Departament, Barcelona Supercomputing Center, Jordi Girona 29, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1145\/209937.209958"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1147\/sj.451.0059"},{"key":"rf14","first-page":"42","volume":"30","author":"Ferrer R.","journal-title":"IEEE Micro"},{"key":"rf26","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-008-0072-7"},{"key":"rf30","doi-asserted-by":"publisher","DOI":"10.1016\/j.jcp.2004.10.011"}],"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626411000151","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T09:30:46Z","timestamp":1565170246000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626411000151"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,6]]},"references-count":5,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2011,6]]}},"alternative-id":["10.1142\/S0129626411000151"],"URL":"https:\/\/doi.org\/10.1142\/s0129626411000151","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,6]]}}}