{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T02:28:07Z","timestamp":1747189687106,"version":"3.40.5"},"reference-count":16,"publisher":"World Scientific Pub Co Pte Ltd","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[2020,12]]},"abstract":"<jats:p> This paper proposes a real-time super-resolution (SR) system. The proposed system performs a fast SR algorithm that generates a high-resolution image from a low-resolution image using direct regression functions with an up-scaling factor of 2. This algorithm contained two processes: feature learning and SR image prediction. The feature learning stage is performed offline, in which several regression functions were trained. The SR image prediction stage is implemented on the proposed system to generate high-resolution image patches. The system implemented on a Xilinx Virtex 7 field-programmable gate array achieves output resolution of [Formula: see text] (UHD) at 85 fps and 700Mpixels\/s throughput. Structure similarity (SSIM) is measured for image quality. Experimental results show that the proposed system provides high image quality for real-time applications. And the proposed system possesses high scalability for resolution. <\/jats:p>","DOI":"10.1142\/s0129626420500115","type":"journal-article","created":{"date-parts":[[2021,1,7]],"date-time":"2021-01-07T09:47:13Z","timestamp":1610012833000},"page":"2050011","source":"Crossref","is-referenced-by-count":0,"title":["A Real-Time Learning-Based Super-Resolution System on FPGA"],"prefix":"10.1142","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5983-119X","authenticated-orcid":false,"given":"Daolu","family":"Zha","sequence":"first","affiliation":[{"name":"School of Physical Sciences, University of Science and Technology of China, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xi","family":"Jin","sequence":"additional","affiliation":[{"name":"School of Physical Sciences, University of Science and Technology of China, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rui","family":"Shang","sequence":"additional","affiliation":[{"name":"Suzhou Graphichina Microelectronics Technology Co., Ltd., Suzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pengfei","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Physical Sciences,University of Science and Technology of China, Hefei, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2021,1,7]]},"reference":[{"key":"S0129626420500115BIB001","first-page":"1419","volume-title":"IEEE International Conference on Image Processing","author":"Choudhury A.","year":"2016"},{"issue":"11","key":"S0129626420500115BIB002","doi-asserted-by":"crossref","first-page":"2861","DOI":"10.1109\/TIP.2010.2050625","volume":"19","author":"Yang J.","year":"2010","journal-title":"IEEE Transactions on Image Processing"},{"key":"S0129626420500115BIB004","first-page":"89","volume-title":"International Conference on Field Programmable Logic and Applications","author":"Bowen O.","year":"2008"},{"issue":"4","key":"S0129626420500115BIB006","doi-asserted-by":"crossref","first-page":"111","DOI":"10.2299\/jsp.17.111","volume":"17","author":"Sanada Y.","year":"2013","journal-title":"Journal of Signal Processing"},{"key":"S0129626420500115BIB007","first-page":"219","volume-title":"IFIP\/IEEE International Conference on Very Large Scale Integration","author":"Seyid K.","year":"2015"},{"key":"S0129626420500115BIB008","first-page":"184","volume-title":"Digital System Design","author":"Redlich R.","year":"2016"},{"volume-title":"IEEE Transactions on Circuits and Systems II Express Briefs","author":"Yang M. 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