{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T09:26:26Z","timestamp":1648977986280},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"01n02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1994,6]]},"abstract":"<jats:p> Term rewriting is a popular computational paradigm for symbolic computations such as formula manipulation, theorem proving and implementations of nonprocedural programming languages. In rewriting, the most demanding operation is repeated simplification of terms by pattern matching them against rewrite rules. We describe a parallel architecture, R<jats:sup>2<\/jats:sup>M, for accelerating this operation. R<jats:sup>2<\/jats:sup>M can operate either as a stand-alone processor using its own memory or as a backend device attached to a host using the host\u2019s main memory. R<jats:sup>2<\/jats:sup>M uses only a fixed number (independent of input size) of processing units and fixed capacity auxiliary memory units, yet it is capable of handling variable-size rewrite rules that change during simplification. This is made possible by a simple and reconfigurable interconnection present in R<jats:sup>2<\/jats:sup>M. Finally, R<jats:sup>2<\/jats:sup>M uses a hybrid scheme that combines the ease, and efficiency of parallel pattern matching using the tree representation of terms, and the naturalness of their dag representation for replacements. <\/jats:p>","DOI":"10.1142\/s0129626494000181","type":"journal-article","created":{"date-parts":[[2004,11,18]],"date-time":"2004-11-18T21:21:13Z","timestamp":1100812873000},"page":"171-180","source":"Crossref","is-referenced-by-count":0,"title":["R<sup>2<\/sup>M: A RECONFIGURABLE REWRITE MACHINE"],"prefix":"10.1142","volume":"04","author":[{"given":"R.","family":"RAMESH","sequence":"first","affiliation":[{"name":"Department of Computer Science, University of Texas at Dallas, Richardson, TX 75083, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626494000181","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T09:31:55Z","timestamp":1565170315000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626494000181"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,6]]},"references-count":0,"journal-issue":{"issue":"01n02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1994,6]]}},"alternative-id":["10.1142\/S0129626494000181"],"URL":"https:\/\/doi.org\/10.1142\/s0129626494000181","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1994,6]]}}}