{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T19:50:43Z","timestamp":1773863443162,"version":"3.50.1"},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1994,12]]},"abstract":"<jats:p> We prove that prefix sums of n integers of at most b bits can be found on a COMMON CRCW PRAM in [Formula: see text] time with a linear time-processor product. The algorithm is optimally fast, for any polynomial number of processors. In particular, if [Formula: see text] the time taken is [Formula: see text]. This is a generalisation of previous result. The previous [Formula: see text] time algorithm was valid only for O(log n)-bit numbers. Application of this algorithm to r-way parallel merge sort algorithm is also considered. <\/jats:p><jats:p> We also consider a more realistic PRAM variant, in which the word size, m, may be smaller than b (m\u2265log n). On this model, prefix sums can be found in [Formula: see text] optimal time. <\/jats:p>","DOI":"10.1142\/s0129626494000399","type":"journal-article","created":{"date-parts":[[2004,11,19]],"date-time":"2004-11-19T02:21:13Z","timestamp":1100830873000},"page":"429-436","source":"Crossref","is-referenced-by-count":6,"title":["ON PARALLEL PREFIX COMPUTATION"],"prefix":"10.1142","volume":"04","author":[{"given":"SANJEEV","family":"SAXENA","sequence":"first","affiliation":[{"name":"Computer Science and Engineering, Indian Institute Of Technology, Kanpur, 208 016, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.C.P.","family":"BHATT","sequence":"additional","affiliation":[{"name":"Micro-elec. and Comp.Sys.Lab., Electrical Enginnering Department, McGill University, 3480 University Street, Montreal (Quebec) H3A 2A7, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.C.","family":"PRASAD","sequence":"additional","affiliation":[{"name":"Electrical Engineering, Indian Institute Of Technology, Delhi, New Delhi, 110 016, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626494000399","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T13:31:43Z","timestamp":1565184703000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626494000399"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1994,12]]},"references-count":0,"journal-issue":{"issue":"04","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1994,12]]}},"alternative-id":["10.1142\/S0129626494000399"],"URL":"https:\/\/doi.org\/10.1142\/s0129626494000399","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1994,12]]}}}