{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T02:43:11Z","timestamp":1648608191446},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1995,3]]},"abstract":"<jats:p> This paper presents a new interconnection network for a massively parallel architecture based on the static model of communication. The principle of the model is to schedule at run time, on a circuit switching hardware, the off-line routed circuits computed at compile time. Designing a network especially for the compiled model can take full benefit of the current interconnection technology. The static network is intended to a synchronised MIMD distributed memory machine, based on high performance processing nodes including microprocessors. The application scope is numerical computation, where all communication patterns may occur. The hardware issues are the various synchronisations inside the network, which need a sophisticated switch design to keep pace with 1.33 Gbit\/s links. The network is designed to reach a sustained aggregate bandwidth of more than 500GBytes\/s, and provide an overall latency less than 270ns, up to 4K inputs. The network is fully pipelined and can be reconfigured each 60ns. <\/jats:p>","DOI":"10.1142\/s0129626495000096","type":"journal-article","created":{"date-parts":[[2004,11,10]],"date-time":"2004-11-10T11:14:37Z","timestamp":1100085277000},"page":"97-109","source":"Crossref","is-referenced-by-count":0,"title":["THE STATIC NETWORK: A HIGH PERFORMANCE RECONFIGURABLE COMMUNICATION NETWORK"],"prefix":"10.1142","volume":"05","author":[{"given":"CECILE","family":"GERMAIN","sequence":"first","affiliation":[{"name":"LRI, Universit\u00e9 Paris-Sud, 91405, Orsay, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"FRANCK","family":"CAPPELLO","sequence":"additional","affiliation":[{"name":"LRI, Universit\u00e9 Paris-Sud, 91405, Orsay, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626495000096","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T16:17:07Z","timestamp":1565108227000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626495000096"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,3]]},"references-count":0,"journal-issue":{"issue":"01","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1995,3]]}},"alternative-id":["10.1142\/S0129626495000096"],"URL":"https:\/\/doi.org\/10.1142\/s0129626495000096","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,3]]}}}