{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T23:59:40Z","timestamp":1648684780096},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Process. Lett."],"published-print":{"date-parts":[[1995,9]]},"abstract":"<jats:p> Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. <\/jats:p><jats:p> In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed-associative cache organization and the semi-unified cache organization are shown to work fine. <\/jats:p>","DOI":"10.1142\/s0129626495000436","type":"journal-article","created":{"date-parts":[[2004,11,10]],"date-time":"2004-11-10T06:14:37Z","timestamp":1100067277000},"page":"475-487","source":"Crossref","is-referenced-by-count":0,"title":["ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS"],"prefix":"10.1142","volume":"05","author":[{"given":"N.","family":"DRACH","sequence":"first","affiliation":[{"name":"LRI, Universit\u00e9 Paris XI, 91405 Orsay Cedex, France"}]},{"given":"A.","family":"GEFFLAUT","sequence":"additional","affiliation":[{"name":"IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France"}]},{"given":"P.","family":"JOUBERT","sequence":"additional","affiliation":[{"name":"IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France"}]},{"given":"A.","family":"SEZNEC","sequence":"additional","affiliation":[{"name":"IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["Parallel Processing Letters"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0129626495000436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T12:18:11Z","timestamp":1565093891000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0129626495000436"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,9]]},"references-count":0,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1995,9]]}},"alternative-id":["10.1142\/S0129626495000436"],"URL":"https:\/\/doi.org\/10.1142\/s0129626495000436","relation":{},"ISSN":["0129-6264","1793-642X"],"issn-type":[{"value":"0129-6264","type":"print"},{"value":"1793-642X","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,9]]}}}