{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T23:09:00Z","timestamp":1648595340747},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int. J. Patt. Recogn. Artif. Intell."],"published-print":{"date-parts":[[1995,4]]},"abstract":"<jats:p> In this paper we present a VLSI fuzzy processor whose main features are a scalable parallel architecture, and the computation of fuzzy inferences based on the \u03b1-level set theory, both of which are important in the field of intensive fuzzy computing, as in fuzzy expert systems. A specific analysis is made in the paper, of techniques for the representation of fuzzy sets, in relation to the amount of area occupied and the forms they can assume. From this analysis a solution is extracted and then used for the processor presented in the paper. <\/jats:p><jats:p> The architecture of the processor is chosen after the assessment of possible alternatives by analyzing an appropriate probabilistic model. The processor comprises a set of units which work parallelly and asynschronously to process the various rules. The structure is easy to scale up, as an increase in the number of processing units does not produce bottlenecks in performance. The performance obtainable is about 310 KFLIPS, with a clock frequency of 60 Mhz, 8 input variables, either crisp or fuzzy, and an 8-bit resolution. <\/jats:p>","DOI":"10.1142\/s0218001495000201","type":"journal-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T11:59:25Z","timestamp":1100260765000},"page":"421-447","source":"Crossref","is-referenced-by-count":2,"title":["A VLSI PARALLEL ARCHITECTURE FOR FUZZY EXPERT SYSTEMS"],"prefix":"10.1142","volume":"09","author":[{"given":"V.","family":"CATANIA","sequence":"first","affiliation":[{"name":"Istituto di Informatica e Telecomunicazione Facolt\u00e0 di Ingegneria-Universit\u00e0 di Catania V.le A.Doria 6, 95125 Catania, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"ASCIA","sequence":"additional","affiliation":[{"name":"Istituto di Informatica e Telecomunicazione Facolt\u00e0 di Ingegneria-Universit\u00e0 di Catania V.le A.Doria 6, 95125 Catania, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["International Journal of Pattern Recognition and Artificial Intelligence"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218001495000201","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T16:38:59Z","timestamp":1565195939000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218001495000201"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,4]]},"references-count":0,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1995,4]]}},"alternative-id":["10.1142\/S0218001495000201"],"URL":"https:\/\/doi.org\/10.1142\/s0218001495000201","relation":{},"ISSN":["0218-0014","1793-6381"],"issn-type":[{"value":"0218-0014","type":"print"},{"value":"1793-6381","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,4]]}}}