{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,30]],"date-time":"2025-03-30T13:27:07Z","timestamp":1743341227657},"reference-count":0,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Int. J. Patt. Recogn. Artif. Intell."],"published-print":{"date-parts":[[1995,4]]},"abstract":"<jats:p> This paper describes the design and the VLSI implementation of a novel architecture that performs image rotation in real time. In order to improve throughput, we divide an image-frame into a number of windows. The rotation of each window-center as well as the final displacement of individual pixels within a window is then calculated. A CORDIC-based scheme is used to compute the displacement of a pixel. Our architectural design is incorporated into a chip that has been laid out using VTI (VLSI Technology Inc.) tools obeying the 1.5 \u03bcm SCMOS design rules. The chip owes its high processing capability to a combination of pipelining and parallel-processing techniques. For a clock frequency greater than 10.6 MHz, we can perform the rotation of a 512\u00d7512 gray-level digital image at the rate of 30 frames per second. The chip utilizes around 35,000 transistors and has an estimated silicon area of 211 mils\u00d7276 mils. <\/jats:p>","DOI":"10.1142\/s0218001495000213","type":"journal-article","created":{"date-parts":[[2004,11,12]],"date-time":"2004-11-12T11:59:25Z","timestamp":1100260765000},"page":"449-462","source":"Crossref","is-referenced-by-count":7,"title":["VLSI IMPLEMENTATION OF AN EFFICIENT ASIC ARCHITECTURE FOR REAL-TIME ROTATION OF DIGITAL IMAGES"],"prefix":"10.1142","volume":"09","author":[{"given":"INDRADEEP","family":"GHOSH","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering Princeton University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"BANDANA","family":"MAJUMDAR","sequence":"additional","affiliation":[{"name":"Department of Electronics and Electrical Communication Engineering Indian Institute of Technology, Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"container-title":["International Journal of Pattern Recognition and Artificial Intelligence"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218001495000213","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T16:38:59Z","timestamp":1565195939000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218001495000213"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1995,4]]},"references-count":0,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[1995,4]]}},"alternative-id":["10.1142\/S0218001495000213"],"URL":"https:\/\/doi.org\/10.1142\/s0218001495000213","relation":{},"ISSN":["0218-0014","1793-6381"],"issn-type":[{"value":"0218-0014","type":"print"},{"value":"1793-6381","type":"electronic"}],"subject":[],"published":{"date-parts":[[1995,4]]}}}