{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T07:17:50Z","timestamp":1767165470315,"version":"build-2238731810"},"reference-count":5,"publisher":"World Scientific Pub Co Pte Ltd","issue":"01n02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2000,2]]},"abstract":"<jats:p>\n                    This paper presents a residue number system to binary converter in the four moduli set {2\n                    <jats:sup>n<\/jats:sup>\n                    - 1, 2\n                    <jats:sup>n<\/jats:sup>\n                    , 2\n                    <jats:sup>n<\/jats:sup>\n                    + 1, 2\n                    <jats:sup>n + 1<\/jats:sup>\n                    - 1}, valid for even values of n. This moduli set is an extension of the popular set {2\n                    <jats:sup>n<\/jats:sup>\n                    - 1, 2\n                    <jats:sup>n<\/jats:sup>\n                    + 1}. The number theoretic properties of the moduli set of the form 2\n                    <jats:sup>n<\/jats:sup>\n                    \u00b1 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.\n                  <\/jats:p>","DOI":"10.1142\/s0218126600000044","type":"journal-article","created":{"date-parts":[[2003,5,7]],"date-time":"2003-05-07T04:18:55Z","timestamp":1052281135000},"page":"85-99","source":"Crossref","is-referenced-by-count":44,"title":["A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2\n                    <sup>n<\/sup>\n                    - 1, 2\n                    <sup>n<\/sup>\n                    , 2\n                    <sup>n<\/sup>\n                    + 1, 2\n                    <sup>n + 1<\/sup>\n                    - 1}"],"prefix":"10.1142","volume":"10","author":[{"given":"A. P","family":"VINOD","sequence":"first","affiliation":[{"name":"School of Computer Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]},{"given":"A. BENJAMIN","family":"PREMKUMAR","sequence":"additional","affiliation":[{"name":"School of Computer Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]}],"member":"219","published-online":{"date-parts":[[2012,4,30]]},"reference":[{"key":"p_4","doi-asserted-by":"publisher","DOI":"10.1109\/81.340862"},{"key":"p_5","first-page":"39","author":"Premkumar A. Benjamin","year":"1992","journal-title":"IEEE Trans. Circuits Syst.-II: Analog and Digital Signal Processing"},{"key":"p_6","first-page":"45","author":"Hiasat Ahmad A.","year":"1998","journal-title":"IEEE Trans. Circuits Syst.-II: Analog and Digital Signal Processing"},{"key":"p_9","first-page":"731","volume":"28","author":"Taylor F.","year":"1981","journal-title":"IEEE Trans. Comput."},{"key":"p_11","first-page":"45","author":"Bharadwaj M.","year":"1998","journal-title":"IEEE Trans. Circuits Syst.-I"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126600000044","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T10:37:32Z","timestamp":1565174252000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126600000044"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,2]]},"references-count":5,"aliases":["10.1016\/s0218-1266(00)00004-4"],"journal-issue":{"issue":"01n02","published-online":{"date-parts":[[2012,4,30]]},"published-print":{"date-parts":[[2000,2]]}},"alternative-id":["10.1142\/S0218126600000044"],"URL":"https:\/\/doi.org\/10.1142\/s0218126600000044","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2000,2]]}}}