{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T22:47:19Z","timestamp":1649026039997},"reference-count":6,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2002,4]]},"abstract":"<jats:p> Four operands Real Multiply Accumulation (4op-RMA) is a method to implement transversal circuits, direct form circuits and 2D type circuits with real coefficients by using a complex multiplier. Digital Signal Processors (DSPs) with 4op-RMA implement these circuits twice as fast as the conventional ones. Besides, we can simplify the programs on such DSPs. However 4op-RMA have not been applied to the lattice circuits yet because of their circuit structures. In this paper, we propose an implementation method for the lattice circuits by using 4op-RMA. The lattice part can be calculated by a 4op-RMA operation, which corresponds to a complex multiplication. <\/jats:p>","DOI":"10.1142\/s0218126602000318","type":"journal-article","created":{"date-parts":[[2003,5,29]],"date-time":"2003-05-29T04:39:54Z","timestamp":1054183194000},"page":"115-121","source":"Crossref","is-referenced-by-count":0,"title":["AN IMPLEMENTATION OF LATTICE FILTERS USING FOUR OPERANDS REAL MULTIPLY ACCUMULATION"],"prefix":"10.1142","volume":"11","author":[{"given":"YOSHIMASA","family":"NEGISHI","sequence":"first","affiliation":[{"name":"Faculty of Systems Engineering, Shibaura Institute of Technology, 307 Fukasaku, Saitama-shi, Saitama 330-8570, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"EIJI","family":"WATANABE","sequence":"additional","affiliation":[{"name":"Faculty of Systems Engineering, Shibaura Institute of Technology, 307 Fukasaku, Saitama-shi, Saitama 330-8570, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"AKINORI","family":"NISHIHARA","sequence":"additional","affiliation":[{"name":"Center for Research and Development of Educational Technology, Tokyo Institute of Technology, 307 Fukasaku,  Saitama-shi, Saitama 330-8570, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"p_1","doi-asserted-by":"publisher","DOI":"10.1109\/31.1776"},{"key":"p_2","first-page":"238","volume":"8","author":"Negishi Y.","year":"1999","journal-title":"IEICE Trans. Fundamentals E82-A"},{"key":"p_3","first-page":"593","author":"Negishi Y.","year":"1999","journal-title":"IEEE ISPACS Proc."},{"key":"p_5","first-page":"6","volume":"33","author":"Shin K.","year":"1998","journal-title":"IEEE J. Solid-State Circuits"},{"key":"p_6","first-page":"674","volume":"8","author":"Aoki T.","year":"1997","journal-title":"IEICE Trans. Inf. Syst. J80-D-I"},{"key":"p_7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052667"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126602000318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T23:44:57Z","timestamp":1565135097000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126602000318"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,4]]},"references-count":6,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2002,4]]}},"alternative-id":["10.1142\/S0218126602000318"],"URL":"https:\/\/doi.org\/10.1142\/s0218126602000318","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2002,4]]}}}