{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T10:43:47Z","timestamp":1648550627369},"reference-count":2,"publisher":"World Scientific Pub Co Pte Lt","issue":"06","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2005,12]]},"abstract":"<jats:p> It has been estimated that multiplexors (MUXes) make up a major portion of the circuitry in a typical chip. Therefore, to reduce power consumption of a chip, it is important to consider the design of MUXes that consumes less power. This is called the low power MUX decomposition problem and has been studied in Ref. 1. This paper improves on the results of Ref. 1 in two ways: (a) we propose a method to speed up the algorithms in Ref. 1, and (b) we propose a post-optimization procedure to further reduce the overall power dissipation of decompositions obtained by any MUX decomposition algorithm. Using this post-optimization procedure, we have been able to further reduce the power dissipation results of Ref. 1. <\/jats:p>","DOI":"10.1142\/s0218126605002866","type":"journal-article","created":{"date-parts":[[2006,2,27]],"date-time":"2006-02-27T09:58:44Z","timestamp":1141034324000},"page":"1085-1099","source":"Crossref","is-referenced-by-count":0,"title":["IMPROVED ALGORITHMS FOR LOW POWER MULTIPLEXOR DECOMPOSITION"],"prefix":"10.1142","volume":"14","author":[{"given":"SHAOFA","family":"YANG","sequence":"first","affiliation":[{"name":"Department of Computer Science, National University of Singapore, 3 Science Drive 2, Singapore 117543, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"HON WAI","family":"LEONG","sequence":"additional","affiliation":[{"name":"Department of Computer Science, National University of Singapore, 3 Science Drive 2, Singapore 117543, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1145\/544536.544539"},{"key":"rf12","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J. L.","year":"2003"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126605002866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:44:00Z","timestamp":1565149440000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126605002866"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,12]]},"references-count":2,"journal-issue":{"issue":"06","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2005,12]]}},"alternative-id":["10.1142\/S0218126605002866"],"URL":"https:\/\/doi.org\/10.1142\/s0218126605002866","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2005,12]]}}}