{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T23:36:19Z","timestamp":1649115379888},"reference-count":27,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2006,2]]},"abstract":"<jats:p> Nowadays, computers are frequently equipped with peripherals that transfer great amounts of data between them and the system memory using direct memory access techniques (i.e., digital cameras, high speed networks, \u2026). Those peripherals prevent the processor from accessing system memory for significant periods of time (i.e., while they are communicating with system memory in order to send or receive data blocks). In this paper we study the negative effects that I\/O operations from computer peripherals have on processor performance. With the help of a set of routines (SMPL) used to make discrete event simulators, we have developed a configurable software that simulates a computer processor and main memory as well as the I\/O scenarios where the peripherals operate. This software has been used to analyze the performance of four different processors in four I\/O scenarios: video capture, video capture and playback, high speed network, and serial transmission. <\/jats:p>","DOI":"10.1142\/s0218126606002927","type":"journal-article","created":{"date-parts":[[2006,4,12]],"date-time":"2006-04-12T06:54:58Z","timestamp":1144824898000},"page":"43-56","source":"Crossref","is-referenced-by-count":1,"title":["INFLUENCE OF INPUT\/OUTPUT OPERATIONS ON PROCESSOR PERFORMANCE"],"prefix":"10.1142","volume":"15","author":[{"given":"JOSE MARIA","family":"RODR\u00cdGUEZ CORRAL","sequence":"first","affiliation":[{"name":"Lenguajes y Sistemas Inform\u00e1ticos, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C\/Chile 1, 11003 C\u00e1diz, Spain"}]},{"given":"ANTON CIVIT","family":"BALCELLS","sequence":"additional","affiliation":[{"name":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s\/n, 41012 Sevilla, Spain"}]},{"given":"GABRIEL JIMENEZ","family":"MORENO","sequence":"additional","affiliation":[{"name":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s\/n, 41012 Sevilla, Spain"}]},{"given":"JOSE LUIS","family":"SEVILLANO RAMOS","sequence":"additional","affiliation":[{"name":"Arquitectura y Tecnolog\u00eda de Computadores, Universidad de Sevilla, Escuela Superior de Ingenier\u00eda Inform\u00e1tica, Avda. Reina Mercedes s\/n, 41012 Sevilla, Spain"}]},{"given":"ARTURO MORGADO","family":"ESTEVEZ","sequence":"additional","affiliation":[{"name":"Ingenier\u00eda de Sistemas y Autom\u00e1tica, Tecnolog\u00eda Electr\u00f3nica y Electr\u00f3nica, Universidad de C\u00e1diz, Escuela Superior de Ingenier\u00eda, C\/Chile 1, 11003 C\u00e1diz, Spain"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","volume-title":"High-Performance Computer Architecture","author":"Stone H. S.","year":"1990"},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/2.84896"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/2.84897"},{"key":"rf4","volume-title":"Computer Architecture. A Quantitative Approach","author":"Hennessy J. L.","year":"2003"},{"key":"rf5","volume":"41","author":"Moreno J. H.","journal-title":"IBM J. Res. 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