{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T10:36:54Z","timestamp":1648809414569},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2006,4]]},"abstract":"<jats:p> A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement. <\/jats:p>","DOI":"10.1142\/s0218126606003027","type":"journal-article","created":{"date-parts":[[2006,8,8]],"date-time":"2006-08-08T10:11:03Z","timestamp":1155031863000},"page":"169-181","source":"Crossref","is-referenced-by-count":0,"title":["RESIZABLE TRANSLATION STORAGE BUFFERS"],"prefix":"10.1142","volume":"15","author":[{"given":"ASSIM","family":"SAGAHYROON","sequence":"first","affiliation":[{"name":"Department of Computer Engineering, American University, Box 26666, Sharjah, UAE"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"AHMED H.","family":"MOHAMED","sequence":"additional","affiliation":[{"name":"Microsoft Corporation, Redmond, Washington, USA 98052, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1109\/40.52948"},{"key":"rf2","volume-title":"Virtual Memory Systems and TLB Structures","author":"Jacob B.","year":"2002"},{"key":"rf3","first-page":"78","volume":"22","author":"Lee R. B.","journal-title":"IEEE Comput."},{"key":"rf6","volume-title":"Higher Performance Computing","author":"Jacob B.","year":"2001"},{"key":"rf13","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J.","year":"1997"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126606003027","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:44:30Z","timestamp":1565149470000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126606003027"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,4]]},"references-count":5,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2006,4]]}},"alternative-id":["10.1142\/S0218126606003027"],"URL":"https:\/\/doi.org\/10.1142\/s0218126606003027","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2006,4]]}}}