{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T06:34:40Z","timestamp":1648622080847},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2006,10]]},"abstract":"<jats:p> Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. <\/jats:p><jats:p> It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. <\/jats:p><jats:p> In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected. <\/jats:p>","DOI":"10.1142\/s0218126606003350","type":"journal-article","created":{"date-parts":[[2007,1,19]],"date-time":"2007-01-19T11:03:50Z","timestamp":1169204630000},"page":"739-756","source":"Crossref","is-referenced-by-count":1,"title":["A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT"],"prefix":"10.1142","volume":"15","author":[{"given":"I.","family":"VOYIATZIS","sequence":"first","affiliation":[{"name":"Department of Informatics, Technological Educational Institute (TEI) of Athens, 12210 Athens, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"KEHAGIAS","sequence":"additional","affiliation":[{"name":"Department of Informatics, Technological Educational Institute (TEI) of Athens, 12210 Athens, Greece"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1978.tb02106.x"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1986.13687"},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1109\/43.41507"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1007\/BF02341826"},{"key":"rf11","volume-title":"Digital Systems Testing and Testable Design","author":"Abramovici M.","year":"1990"},{"key":"rf12","volume-title":"Built-In Test for VLSI: Pseudorandom Techniques","author":"Bardell P.","year":"1987"},{"key":"rf20","doi-asserted-by":"publisher","DOI":"10.1109\/43.720322"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126606003350","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T17:55:55Z","timestamp":1565200555000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126606003350"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10]]},"references-count":7,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2006,10]]}},"alternative-id":["10.1142\/S0218126606003350"],"URL":"https:\/\/doi.org\/10.1142\/s0218126606003350","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2006,10]]}}}