{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T09:19:51Z","timestamp":1648631991094},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"01","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2007,2]]},"abstract":"<jats:p> In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-\u03bcm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems. <\/jats:p>","DOI":"10.1142\/s0218126607003551","type":"journal-article","created":{"date-parts":[[2007,5,21]],"date-time":"2007-05-21T07:43:34Z","timestamp":1179733414000},"page":"1-14","source":"Crossref","is-referenced-by-count":0,"title":["SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION"],"prefix":"10.1142","volume":"16","author":[{"given":"TASKIN","family":"KOCAK","sequence":"first","affiliation":[{"name":"School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, Florida 32816-2450, USA"}]},{"given":"GEORGE R.","family":"HARRIS","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, Florida 32816-2450, USA"}]},{"given":"RONALD F.","family":"DEMARA","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, University of Central Florida, Orlando, Florida 32816-2450, USA"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"rf5","volume-title":"Asynchronous Sequential Switching Circuits","author":"Unger S. H.","year":"1969"},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2003.12.004"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1109\/92.831441"},{"key":"rf13","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19990544"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1109\/4.839925"},{"key":"rf18","volume-title":"The Data Conversion Handbook","author":"Kaster W.","year":"2005"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126607003551","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T23:41:44Z","timestamp":1565134904000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126607003551"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,2]]},"references-count":8,"journal-issue":{"issue":"01","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2007,2]]}},"alternative-id":["10.1142\/S0218126607003551"],"URL":"https:\/\/doi.org\/10.1142\/s0218126607003551","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,2]]}}}