{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T00:04:32Z","timestamp":1648944272449},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2007,6]]},"abstract":"<jats:p> A full-scan structure is described, in which the classic single serial scan-path and the parallel-in\/serial-out scan (PASE-Scan) designs coexist. It requires only one extra pin and a small hardware overhead with respect to the single serial scan-path approach, and is compatible with a test scheme of this type. A method for the structure design is outlined and a structure-oriented optimized procedure for obtaining the test is proposed which considerably reduces the test application cost with respect to the serial scan case, improving the previous results for parallel-serial designs. The experiments performed with the ISCAS89 benchmarks show average reductions in test length of 60.6% with respect to its full serial scan counterpart and of 58.7%, with respect to a conventional full serial scan test with normal compaction. The advantage of the COMPASES scheme in testing some circuits with multiple PASE-Scan structures is also outlined. <\/jats:p>","DOI":"10.1142\/s0218126607003678","type":"journal-article","created":{"date-parts":[[2007,10,11]],"date-time":"2007-10-11T10:04:36Z","timestamp":1192097076000},"page":"467-488","source":"Crossref","is-referenced-by-count":0,"title":["COMPASES: AN OPTIMIZED DESIGN FOR TESTABILITY SCHEME TO REDUCE THE COST OF TEST APPLICATION USING PARALLEL-SERIAL SCAN DESIGN"],"prefix":"10.1142","volume":"16","author":[{"given":"JOS\u00c9 M.","family":"SOLANA","sequence":"first","affiliation":[{"name":"Departamento de Electr\u00f3nica y Computadores, Universidad de Cantabria, 39005-Santander, Spain"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19951520"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1109\/12.241600"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1109\/43.387735"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/43.256936"},{"key":"rf13","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19990812"},{"key":"rf14","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20000188"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1049\/el:20010868"},{"key":"rf18","first-page":"769","volume":"35","author":"Abramovici M.","journal-title":"IEEE Trans. Comput. C"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126607003678","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:41:42Z","timestamp":1565149302000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126607003678"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6]]},"references-count":8,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2007,6]]}},"alternative-id":["10.1142\/S0218126607003678"],"URL":"https:\/\/doi.org\/10.1142\/s0218126607003678","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,6]]}}}