{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T20:01:14Z","timestamp":1649188874449},"reference-count":9,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2007,8]]},"abstract":"<jats:p> This paper proposes an interactive architecture compiler for SC multirate circuits that allows the automated design from the frequency specifications to the building block implementation, applied to the design and synthesis of multistage SC decimators. The compiler provides a library of different topologies that comprises a few independent multi-decimation building blocks. New building blocks defined by the users are also available for the design of a specific stage. A design example of a 7th order SC decimator illustrates the efficient synthesis of the corresponding resulting circuits that achieve the required anti-aliasing amplitude responses with respect to the speed requirements of the operational amplifiers and also the minimum capacitance spread and total capacitor area. <\/jats:p>","DOI":"10.1142\/s0218126607003770","type":"journal-article","created":{"date-parts":[[2007,12,11]],"date-time":"2007-12-11T06:08:12Z","timestamp":1197353292000},"page":"517-525","source":"Crossref","is-referenced-by-count":1,"title":["INTERACTIVE IIR SC MULTIRATE COMPILER APPLIED TO MULTISTAGE DECIMATOR DESIGN"],"prefix":"10.1142","volume":"16","author":[{"given":"PHILLIP N.","family":"CHEONG","sequence":"first","affiliation":[{"name":"Computer Studies Program, Macau Polytechnic Institute, Rua de Lu Gonzaga Gomes, Macau, P. R. China"}]},{"given":"R. P.","family":"MARTINS","sequence":"additional","affiliation":[{"name":"Faculty of Science and Technology, University of Macau, Av. Padre Tom\u00e1s Pereira S. J., Taipa, Macao, P. R. China"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","volume-title":"Analogue-Digital ASICs, Circuit Techniques, Design Tools and Applications","author":"Horta N. C.","year":"1991"},{"key":"rf2","first-page":"5","author":"Nairn D. G.","journal-title":"IEEE Circuits Dev. Mag."},{"key":"rf4","doi-asserted-by":"crossref","first-page":"962","DOI":"10.1109\/4.236176","volume":"28","author":"Martins R. P.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/81.401146"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/82.481472"},{"key":"rf7","doi-asserted-by":"crossref","DOI":"10.1016\/0165-1684(83)90013-0","volume-title":"Multirate Digital Signal Processing","author":"Crochiere R.","year":"1983"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.801208"},{"key":"rf11","first-page":"858","volume":"14","author":"Fino M. H.","journal-title":"IEEE Trans. CAD\/ICAS"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1049\/el:19930635"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126607003770","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T13:56:09Z","timestamp":1565186169000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126607003770"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8]]},"references-count":9,"journal-issue":{"issue":"04","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2007,8]]}},"alternative-id":["10.1142\/S0218126607003770"],"URL":"https:\/\/doi.org\/10.1142\/s0218126607003770","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,8]]}}}