{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T17:26:31Z","timestamp":1649179591383},"reference-count":6,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2008,4]]},"abstract":"<jats:p> A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V V<jats:sub>DD<\/jats:sub> and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 \u00d7 8 \u00d7 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 \u03bcm process and the power consumption can be further reduced using the more downsized technology designs. <\/jats:p>","DOI":"10.1142\/s0218126608004307","type":"journal-article","created":{"date-parts":[[2008,11,27]],"date-time":"2008-11-27T13:36:08Z","timestamp":1227792968000},"page":"211-219","source":"Crossref","is-referenced-by-count":0,"title":["LOW POWER ADIABATIC PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK IAPDL"],"prefix":"10.1142","volume":"17","author":[{"given":"W. J.","family":"YANG","sequence":"first","affiliation":[{"name":"Center for Integrated Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]},{"given":"Y.","family":"ZHOU","sequence":"additional","affiliation":[{"name":"Center for Integrated Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]},{"given":"K. T.","family":"LAU","sequence":"additional","affiliation":[{"name":"Center for Integrated Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","volume-title":"Digital Integrated Circuits \u2014 A Design Perspective","author":"Rabaey J. M.","year":"2003"},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19951345"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1049\/el:19971454"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2692(99)00105-6"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/4.364447"},{"key":"rf7","volume-title":"Basic VLSI Design","author":"Pucknell D.","year":"1994"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126608004307","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:42:41Z","timestamp":1565149361000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126608004307"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,4]]},"references-count":6,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2008,4]]}},"alternative-id":["10.1142\/S0218126608004307"],"URL":"https:\/\/doi.org\/10.1142\/s0218126608004307","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,4]]}}}