{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T15:02:00Z","timestamp":1648998120308},"reference-count":26,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2009,11]]},"abstract":"<jats:p> Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield. <\/jats:p>","DOI":"10.1142\/s0218126609005617","type":"journal-article","created":{"date-parts":[[2009,10,8]],"date-time":"2009-10-08T06:01:28Z","timestamp":1254981688000},"page":"1185-1204","source":"Crossref","is-referenced-by-count":2,"title":["A DIRECT SEARCH METHOD FOR WORST CASE ANALYSIS AND YIELD OPTIMIZATION OF INTEGRATED CIRCUITS"],"prefix":"10.1142","volume":"18","author":[{"given":"GREGOR","family":"CIJAN","sequence":"first","affiliation":[{"name":"Regional Development Agency of Northern Primorska, Mednarodni Prehod 6, SI-5290 \u0160empeter pri Gorici, Slovenia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"TADEJ","family":"TUMA","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering, University of Ljubljana, Tr\u017ea\u0161ka 25, SI-1000 Ljubljana, Slovenia"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"\u00c1RP\u00c1D","family":"B\u0170RMEN","sequence":"additional","affiliation":[{"name":"Faculty of Electrical Engineering, University of Ljubljana, Tr\u017ea\u0161ka 25, SI-1000 Ljubljana, Slovenia"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","unstructured":"H. E.\u00a0Graeb, Analog Design Centering and Sizing (Springer, Dordrecht, 2007)\u00a0p. 195."},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882513"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/43.372370"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852037"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/4235.752918"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.06.001"},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1109\/43.273749"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1049\/el:19760385"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084699"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1016\/S0377-0427(00)00423-4"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1137\/S1052623498339727"},{"key":"rf13","doi-asserted-by":"publisher","DOI":"10.1078\/1434-8411-54100139"},{"key":"rf14","doi-asserted-by":"publisher","DOI":"10.1109\/43.856971"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052648"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1109\/4.127338"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008330121404"},{"key":"rf19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011237602078"},{"key":"rf20","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-006-9705-1"},{"key":"rf21","doi-asserted-by":"publisher","DOI":"10.1137\/S1052623403433638"},{"key":"rf23","doi-asserted-by":"publisher","DOI":"10.1145\/321062.321069"},{"key":"rf24","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008256724276"},{"key":"rf27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"rf28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848021"},{"key":"rf29","unstructured":"J.\u00a0Nocedal and S. J.\u00a0Wright, Numerical Optimization (Springer Science+Business Media, New York, 2006)\u00a0p. 664."},{"key":"rf30","doi-asserted-by":"publisher","DOI":"10.1109\/9780470547106"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126609005617","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T23:54:16Z","timestamp":1565135656000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126609005617"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":26,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2009,11]]}},"alternative-id":["10.1142\/S0218126609005617"],"URL":"https:\/\/doi.org\/10.1142\/s0218126609005617","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,11]]}}}