{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T11:34:44Z","timestamp":1648726484881},"reference-count":8,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2009,11]]},"abstract":"<jats:p> Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption. <\/jats:p>","DOI":"10.1142\/s0218126609005630","type":"journal-article","created":{"date-parts":[[2009,10,8]],"date-time":"2009-10-08T06:01:28Z","timestamp":1254981688000},"page":"1227-1241","source":"Crossref","is-referenced-by-count":0,"title":["A RECONFIGURABLE MODULAR ARCHITECTURE TO EXPLOIT WORD-LEVEL PARALLELISM"],"prefix":"10.1142","volume":"18","author":[{"given":"DANIEL J.","family":"CARBALLO","sequence":"first","affiliation":[{"name":"Dpto. Arquitectura de Computadores y Automatica, University Complutense de Madrid, Madrid, 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"INMACULADA","family":"PARDINES","sequence":"additional","affiliation":[{"name":"Dpto. Arquitectura de Computadores y Automatica, University Complutense de Madrid, Madrid, 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"MARCOS","family":"SANCHEZ-ELEZ","sequence":"additional","affiliation":[{"name":"Dpto. Arquitectura de Computadores y Automatica, University Complutense de Madrid, Madrid, 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","first-page":"43","author":"Diefendorff K.","journal-title":"IEEE Computer"},{"key":"rf3","first-page":"86","author":"Waingold E.","journal-title":"IEEE Computer"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1145\/605459.605461"},{"key":"rf9","doi-asserted-by":"crossref","DOI":"10.1201\/9781482276046","volume-title":"Digital Signal Processing for Multimedia Systems","author":"Parhi K.","year":"1999"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831478"},{"key":"rf17","doi-asserted-by":"publisher","DOI":"10.1049\/ecej:19950606"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1109\/79.952804"},{"key":"rf20","doi-asserted-by":"publisher","DOI":"10.1142\/9781860949630_0042"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126609005630","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T23:54:19Z","timestamp":1565135659000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126609005630"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,11]]},"references-count":8,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2009,11]]}},"alternative-id":["10.1142\/S0218126609005630"],"URL":"https:\/\/doi.org\/10.1142\/s0218126609005630","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,11]]}}}