{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T17:37:48Z","timestamp":1649180268485},"reference-count":10,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2010,4]]},"abstract":"<jats:p> This paper presents a low-power 10-bit 200 MS\/s pipelined ADC in a 90 nm CMOS technology with 1 V supply voltage. To decrease the power dissipation efficiently, a new architecture using a combination of two power reduction techniques named double-sampling and opamp-sharing has been used to reduce the power consumption significantly, without any degradation in the performance of the ADC. In addition, the stage scaling technique has been applied to the ADC efficiently, and two-stage class A\/AB and class A amplifiers and dynamic comparators have been used in sample and hold and sub-ADCs. According to HSPICE simulation results, the 10-bit 200 MSample\/s pipeline ADC with a 9.375 MHz, 1-V<jats:sub>P-P,diff<\/jats:sub> input signal in a 90 nm CMOS process achieves a SNDR of 58.5 dB while consuming only 30.9 mW power from a 1 V supply voltage. <\/jats:p>","DOI":"10.1142\/s021812661000613x","type":"journal-article","created":{"date-parts":[[2010,3,3]],"date-time":"2010-03-03T09:31:10Z","timestamp":1267608670000},"page":"393-405","source":"Crossref","is-referenced-by-count":2,"title":["A LOW-VOLTAGE LOW-POWER 10-BIT 200 MS\/S PIPELINED ADC IN 90 NM CMOS"],"prefix":"10.1142","volume":"19","author":[{"given":"SAHEL","family":"ABDINIA","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, K. N. Toosi University of Technology, Tehran, Iran"}]},{"given":"MOHAMMAD","family":"YAVARI","sequence":"additional","affiliation":[{"name":"Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","first-page":"2031","volume":"38","author":"Min B.-M.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873888"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922718"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/4.494191"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20040414"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864131"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/4.910473"},{"key":"rf13","doi-asserted-by":"crossref","first-page":"157","DOI":"10.1109\/ISCAS.2002.1010664","volume":"5","author":"Sumanen L.","journal-title":"IEEE Int. Symp. Circuits and Systems"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917470"},{"key":"rf17","first-page":"1161","volume":"88","author":"Yavari M.","journal-title":"IEICE Trans. Electron. E"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S021812661000613X","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:52:50Z","timestamp":1565149970000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S021812661000613X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4]]},"references-count":10,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2010,4]]}},"alternative-id":["10.1142\/S021812661000613X"],"URL":"https:\/\/doi.org\/10.1142\/s021812661000613x","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,4]]}}}