{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,10,10]],"date-time":"2023-10-10T01:23:55Z","timestamp":1696901035911},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"08","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2010,12]]},"abstract":"<jats:p> A hybrid continuous-time (CT)\/discrete-time (DT) multi-stage noise-shaping (MASH) \u03a3\u0394 modulator architecture is presented. The double-sampling technique is employed in the DT second stage modulator. A flat and a unity signal transfer functions (STFs) are used in the first and second stage modulators, respectively, to make the modulator robust to nonlinearities of the analog circuitry and well suited for low-voltage applications without influencing the inherent anti-aliasing behavior of the first stage CT modulator. Unlike the conventional MASH architecture, this structure is insensitive to the amplifier limited DC gain of CT stage and avoids the need of compensation for finite gain-bandwidth induced error in CT loop filter. Behavioral simulations confirm the effectiveness of the proposed scheme over existing cascaded topologies. <\/jats:p>","DOI":"10.1142\/s0218126610007018","type":"journal-article","created":{"date-parts":[[2010,12,6]],"date-time":"2010-12-06T09:10:55Z","timestamp":1291626655000},"page":"1743-1751","source":"Crossref","is-referenced-by-count":2,"title":["LOW-VOLTAGE DOUBLE-SAMPLED HYBRID CT\/DT \u03a3\u0394 MODULATOR FOR WIDEBAND APPLICATIONS"],"prefix":"10.1142","volume":"19","author":[{"given":"MOHAMMAD HOSSEIN","family":"MAGHAMI","sequence":"first","affiliation":[{"name":"Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran"}]},{"given":"MOHAMMAD","family":"YAVARI","sequence":"additional","affiliation":[{"name":"Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran"}]}],"member":"219","published-online":{"date-parts":[[2011,11,21]]},"reference":[{"key":"rf1","first-page":"796","author":"Kulchycki S. D.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf3","first-page":"314","author":"Yavari M.","journal-title":"IEEE Trans. Circuits Syst.-II: Express Briefs"},{"key":"rf4","first-page":"75","author":"Yan S.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf5","first-page":"2212","author":"Maghari N.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf6","volume-title":"Continuous-Time Sigma-Delta A\/D Conversion","author":"Ortmanns M.","year":"2005"},{"key":"rf7","volume":"41","author":"Maeyer J.","journal-title":"Electronics Letters"},{"key":"rf9","first-page":"157","author":"Rombouts P.","journal-title":"IEEE Trans. Circuits Syst.-II: Analog Digit. Signal Process."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126610007018","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T03:53:07Z","timestamp":1565149987000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126610007018"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12]]},"references-count":7,"journal-issue":{"issue":"08","published-online":{"date-parts":[[2011,11,21]]},"published-print":{"date-parts":[[2010,12]]}},"alternative-id":["10.1142\/S0218126610007018"],"URL":"https:\/\/doi.org\/10.1142\/s0218126610007018","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12]]}}}