{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T12:36:40Z","timestamp":1649162200223},"reference-count":12,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2011,4]]},"abstract":"<jats:p> With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. A dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications. This paper presents dual-threshold voltage technique for reducing leakage power dissipation of Quasi Delay Insensitive asynchronous pipelines while still maintaining high performance of these circuits. We exploited the Dependency Graph model to produce a formal performance analysis. In order to reduce leakage power an efficient algorithm for selecting and assigning high threshold voltage to templates of a pipeline is proposed. Results obtained indicate that our proposed technique can achieve on average 40% savings for leakage power, while there is no performance penalty. <\/jats:p>","DOI":"10.1142\/s0218126611007207","type":"journal-article","created":{"date-parts":[[2011,3,10]],"date-time":"2011-03-10T03:22:59Z","timestamp":1299727379000},"page":"207-222","source":"Crossref","is-referenced-by-count":0,"title":["LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES"],"prefix":"10.1142","volume":"20","author":[{"given":"BEHNAM","family":"GHAVAMI","sequence":"first","affiliation":[{"name":"Computer Engineering Department, Amirkabir University of Technology Tehran, Iran"}]},{"given":"HOSSEIN","family":"PEDRAM","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, Amirkabir University of Technology Tehran, Iran"}]},{"given":"AREZOO","family":"SALARPOUR","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, Amirkabir University of Technology Tehran, Iran"}]}],"member":"219","published-online":{"date-parts":[[2012,4,30]]},"reference":[{"key":"rf2","volume":"6","author":"Rahbaran B.","journal-title":"IEEE Trans. Dependable and Secure Computing"},{"key":"rf4","volume":"15","author":"Singh M.","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126609005642"},{"key":"rf8","first-page":"23","volume":"19","author":"Agarwal A.","journal-title":"IEEE Micro"},{"key":"rf9","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035575"},{"key":"rf13","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511674730"},{"key":"rf14","volume":"25","author":"Kim S.","journal-title":"IEEE Trans. Comput-aided Des. Integr. Circuits Syst."},{"key":"rf15","author":"Raji M.","journal-title":"Microelectron. J."},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126698000055"},{"key":"rf19","volume-title":"Digital Integrated Circuits","author":"Rabaey J. M.","year":"1996"},{"key":"rf20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052773"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126611007207","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T10:21:20Z","timestamp":1565173280000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126611007207"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":12,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2012,4,30]]},"published-print":{"date-parts":[[2011,4]]}},"alternative-id":["10.1142\/S0218126611007207"],"URL":"https:\/\/doi.org\/10.1142\/s0218126611007207","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,4]]}}}