{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T18:29:27Z","timestamp":1649183367897},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2011,8]]},"abstract":"<jats:p> The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. High power consumption can be reduced by properly increasing area. However, arbitrarily large area, namely high number of functional units (FU) in high-level view, dramatically increases IC cost. This paper describes a new dynamic-power aware High Level Synthesis data path approach that considers dynamic FU allocation while attempting to minimize area, power, or make a trade-off between them. The experimental results have shown that when the area is nearly the same, our approach delivers a 5.99% reduction in power consumption. And when the power consumption is nearly the same, a 11.81% reduction in total FU area occurs. And we can obtain different optimal power\u2013area trade-off values by adjusting power and area ratios. <\/jats:p>","DOI":"10.1142\/s0218126611007682","type":"journal-article","created":{"date-parts":[[2011,4,12]],"date-time":"2011-04-12T22:22:11Z","timestamp":1302646931000},"page":"915-925","source":"Crossref","is-referenced-by-count":1,"title":["A NEW DYNAMIC FUNCTIONAL UNIT ALLOCATION STRATEGY IN HIGH-LEVEL SYNTHESIS TO ACHIEVE POWER\u2013AREA TRADE-OFFS"],"prefix":"10.1142","volume":"20","author":[{"given":"FENG","family":"WU","sequence":"first","affiliation":[{"name":"School of Computer Science and Technology, Wuhan University of Technology, 122 Luoshi Road, Wuhan, Hubei, Wuhan, 430070, P. R. China"}]},{"given":"NING","family":"XU","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Wuhan University of Technology, 122 Luoshi Road, Wuhan, Hubei, Wuhan, 430070, P. R. China"}]}],"member":"219","published-online":{"date-parts":[[2012,4,30]]},"reference":[{"key":"rf3","first-page":"1260","volume":"25","author":"Raghunathan A.","journal-title":"IEEE Trans. CAD Integr. Circuits Syst."},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810796"},{"key":"rf6","first-page":"1113","author":"Chabini N.","journal-title":"IEEE Trans. VLSI"},{"key":"rf8","author":"Rettberg A.","journal-title":"Proc. DELTA"},{"key":"rf9","unstructured":"P.\u00a0Coussy and A.\u00a0Morawiec, High-Level Synthesis Algorithms for Power and Temperature Minimization, eds. L.\u00a0Shang, R. P.\u00a0Dick and N. K.\u00a0Jha (France, 2008)\u00a0pp. 285\u2013287."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126611007682","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T13:54:45Z","timestamp":1565099685000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126611007682"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8]]},"references-count":5,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2012,4,30]]},"published-print":{"date-parts":[[2011,8]]}},"alternative-id":["10.1142\/S0218126611007682"],"URL":"https:\/\/doi.org\/10.1142\/s0218126611007682","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8]]}}}