{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T09:58:44Z","timestamp":1742378324107},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2011,11]]},"abstract":"<jats:p> An original low-power low-voltage multifunctional structure with improved performances will be further presented, allowing to implement (with minor changes in the design) four important functions: the signal gain with theoretical null distortions, voltage multiplying with very good linearity and simulation of a perfect linear resistor with both positive and negative equivalent resistance. The linearity will be strongly increased by implementing original techniques, while the silicon occupied area per function will be reduced as a result of the circuit multifunctionality. The structure is implemented in 0.35 \u03bcm CMOS technology and is supplied at \u00b13 V. The circuit presents a very good linearity (THD &lt; 0.1% for differential amplifier and active resistors and THD &lt; 0.15% for multiplier), correlated with an extended range of the input voltage (-1.5 V &lt; v<jats:sub>1<\/jats:sub> - v<jats:sub>2<\/jats:sub> &lt; 1.5 V ). The tuning range of the active resistor is about 100k\u03a9 \u2013 1.5M\u03a9. The second-order effects are also considered, being proposed an original technique based on an anti-parallel connection for compensating the linearity degradation introduced by these effects. <\/jats:p>","DOI":"10.1142\/s0218126611007876","type":"journal-article","created":{"date-parts":[[2011,12,9]],"date-time":"2011-12-09T05:44:34Z","timestamp":1323409474000},"page":"1261-1275","source":"Crossref","is-referenced-by-count":2,"title":["MULTIFUNCTIONAL CMOS STRUCTURE WITH IMPROVED LINEARITY"],"prefix":"10.1142","volume":"20","author":[{"given":"COSMIN","family":"POPA","sequence":"first","affiliation":[{"name":"Faculty of Electronics, Telecommunications and Information Technology, University Politehnica of Bucharest, Romania"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2012,4,30]]},"reference":[{"key":"rf3","first-page":"1314","volume":"41","author":"Jongchan K.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.809520"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.899242"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2006.873805"},{"key":"rf15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.899242"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126611007876","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T13:55:09Z","timestamp":1565099709000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126611007876"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":5,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2012,4,30]]},"published-print":{"date-parts":[[2011,11]]}},"alternative-id":["10.1142\/S0218126611007876"],"URL":"https:\/\/doi.org\/10.1142\/s0218126611007876","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,11]]}}}