{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T04:35:43Z","timestamp":1648701343844},"reference-count":1,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2012,4]]},"abstract":"<jats:p> Transactional memory addresses a number of important issues in lock-based parallel programs. Unfortunately, the semantics of transactions are different from those of critical sections defined by locks. The semantic differences make it difficult to correctly port existing lock-based programs to transaction-based programs. Experienced programmers accustomed to lock-based programming can easily make mistakes in transaction-based programming as parallel programs running correctly using locks can run incorrectly when critical sections are converted to using transactions. This problem becomes even more severe in porting lock-based programs to use the efficient software transactional memory. In this paper, we first identify three necessary properties in a program for the program execution using transactions to be equivalent to the program execution using locks. Assuming that the input lock-based program satisfies the necessary properties (i.e., a well-behaved parallel program), we next present a correctness condition to verify the transactional memory implementation in order for the program execution using transactions to be equivalent to the program execution using locks. Finally, we develop a correct and efficient software transactional memory implementation that satisfies the correctness condition so that locks in the well-behaved parallel programs can be converted to use the efficient software transactional memory easily and correctly. <\/jats:p>","DOI":"10.1142\/s0218126612400051","type":"journal-article","created":{"date-parts":[[2012,6,11]],"date-time":"2012-06-11T02:35:07Z","timestamp":1339382107000},"page":"1240005","source":"Crossref","is-referenced-by-count":0,"title":["FROM LOCKS TO CORRECT AND EFFICIENT TRANSACTIONAL MEMORY"],"prefix":"10.1142","volume":"21","author":[{"given":"CHENG","family":"WANG","sequence":"first","affiliation":[{"name":"Programming Systems Lab\/Microprocessor and Programming Research Intel Labs, 2200 Mission College Blvd., Santa Clara, CA 95052, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"YOUFENG","family":"WU","sequence":"additional","affiliation":[{"name":"Programming Systems Lab\/Microprocessor and Programming Research Intel Labs, 2200 Mission College Blvd., Santa Clara, CA 95052, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2012,6,11]]},"reference":[{"key":"p_9","first-page":"42","author":"Shpeisman T.","year":"2007","journal-title":"SIGPLAN Not."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126612400051","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T04:06:20Z","timestamp":1565150780000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126612400051"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":1,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2012,6,11]]},"published-print":{"date-parts":[[2012,4]]}},"alternative-id":["10.1142\/S0218126612400051"],"URL":"https:\/\/doi.org\/10.1142\/s0218126612400051","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,4]]}}}