{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T13:11:22Z","timestamp":1719839482223},"reference-count":18,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2012,8]]},"abstract":"<jats:p> With reference to an architecture for the full integration of a 60 GHz receiver in embedded systems with wireless gigabit connectivity, the paper presents the design of key building blocks such as: on-chip antenna, low noise amplifier (LNA) and a time-interleaved fast A\/D converter (ADC) with AMBA AXI interface towards the digital baseband part. With respect to the state of the art the co-design of the on-chip antenna with the LNA, and the fast ADC architecture realized as a time-interleaved array of threshold-configuring SAR channels, represent new solutions optimized in terms of power consumption. Complexity and performance results in a 65-nm CMOS SOI technology, suitable also for digital systems integration, are presented. The performance and complexity results of the designed antenna, LNA and ADC are integrated in a system level simulator with those obtained by adopting known solutions for other receiver blocks (mixer, IF and baseband amplifiers and filters, frequency synthesizer) thus estimating the performance achievable with a whole 60 GHz receiver and digitization sub-system macrocell. The system-level estimated performances confirm the feasibility of a full-integrated receiver supporting short-range High Definition (HD) connectivity of several Gb\/s with a Signal-to-Noise-Ratio compliant with WiGig and Wireless HD new standardization initiatives. <\/jats:p>","DOI":"10.1142\/s0218126612500478","type":"journal-article","created":{"date-parts":[[2012,8,31]],"date-time":"2012-08-31T03:44:10Z","timestamp":1346384650000},"page":"1250047","source":"Crossref","is-referenced-by-count":8,"title":["INTEGRATED 60 GHZ ANTENNA, LNA AND FAST ADC ARCHITECTURE FOR EMBEDDED SYSTEMS WITH WIRELESS GBIT CONNECTIVITY"],"prefix":"10.1142","volume":"21","author":[{"given":"SERGIO","family":"SAPONARA","sequence":"first","affiliation":[{"name":"Department of Information Engineering, University of Pisa, via Caruso 16, I-56122, Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"BRUNO","family":"NERI","sequence":"additional","affiliation":[{"name":"Department of Information Engineering, University of Pisa, via Caruso 16, I-56122, Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2012,9,18]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.318"},{"key":"rf12","first-page":"843","volume":"92","author":"Saponara S.","journal-title":"IEICE Trans. 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