{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:12:51Z","timestamp":1758892371855},"reference-count":3,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2013,3]]},"abstract":"<jats:p> Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes \u2014 one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%\/86.84% of the average power in write\/read-operation of configuration cache compared to the previous design. <\/jats:p>","DOI":"10.1142\/s0218126613500011","type":"journal-article","created":{"date-parts":[[2013,2,20]],"date-time":"2013-02-20T03:28:54Z","timestamp":1361330934000},"page":"1350001","source":"Crossref","is-referenced-by-count":3,"title":["POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE"],"prefix":"10.1142","volume":"22","author":[{"given":"YOONJIN","family":"KIM","sequence":"first","affiliation":[{"name":"Department of Computer Science, Sookmyung Women's University, Seoul, 140-742, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2013,3,26]]},"reference":[{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1145\/780731.780758"},{"key":"rf13","first-page":"26","volume":"20","author":"Lee J.-E.","year":"2003","journal-title":"IEEE Design Test Comput."}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126613500011","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T20:46:28Z","timestamp":1565124388000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126613500011"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":3,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2013,3,26]]},"published-print":{"date-parts":[[2013,3]]}},"alternative-id":["10.1142\/S0218126613500011"],"URL":"https:\/\/doi.org\/10.1142\/s0218126613500011","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}