{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T12:40:58Z","timestamp":1648989658747},"reference-count":7,"publisher":"World Scientific Pub Co Pte Lt","issue":"03","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2013,3]]},"abstract":"<jats:p> The cascode amplifier has the potential of providing high gain and high bandwidth simultaneously. However, the design is not as intuitive as one might at first think. In this paper, we present a detailed analysis of the single cascode amplifiers. The relationship between gain and bandwidth is important. When used to achieve maximum bandwidth the voltage gain of the common-source stage is close to unity. However, when the cascode is designed to obtain a high voltage gain, then the gain-bandwidth trade-off, typical in the common source amplifier, reappears. This analysis is used to provide the basis for practical cascode amplifier design. <\/jats:p>","DOI":"10.1142\/s0218126613500138","type":"journal-article","created":{"date-parts":[[2013,3,12]],"date-time":"2013-03-12T11:34:56Z","timestamp":1363088096000},"page":"1350013","source":"Crossref","is-referenced-by-count":0,"title":["GAIN-BANDWIDTH TRADE-OFF IN THE CMOS CASCODE AMPLIFIER"],"prefix":"10.1142","volume":"22","author":[{"given":"M.","family":"BEN-ESMAEL","sequence":"first","affiliation":[{"name":"Department of Computing and Communication, Oxford Brookes, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F. J.","family":"LIDGEY","sequence":"additional","affiliation":[{"name":"Department of Computing and Communication, Oxford Brookes, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"HAYATLEH","sequence":"additional","affiliation":[{"name":"Department of Computing and Communication, Oxford Brookes, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B. L.","family":"HART","sequence":"additional","affiliation":[{"name":"Department of Computing and Communication, Oxford Brookes, Oxford, OX33 1HX, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2013,3,26]]},"reference":[{"key":"rf1","volume-title":"Analysis and Design of Analog Integrated Circuits","author":"Gray P.","year":"2010"},{"key":"rf2","volume-title":"CMOS Analog Circuit Design","author":"Allen P.","year":"2010"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511807121"},{"key":"rf4","volume-title":"Analog Integrated Circuit Design","author":"Carusone T.","year":"2011"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511807121"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511803840"},{"key":"rf7","volume-title":"Design of Analog CMOS Integrated Circuits","author":"Razavi J. B.","year":"2003"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126613500138","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T20:46:52Z","timestamp":1565124412000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126613500138"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":7,"journal-issue":{"issue":"03","published-online":{"date-parts":[[2013,3,26]]},"published-print":{"date-parts":[[2013,3]]}},"alternative-id":["10.1142\/S0218126613500138"],"URL":"https:\/\/doi.org\/10.1142\/s0218126613500138","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}