{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T00:34:52Z","timestamp":1648514092838},"reference-count":11,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2013,6]]},"abstract":"<jats:p> The Time-Multiplexed FPGA (TMFPGA) architecture can improve dramatically logic utilization by time-sharing logic but it needs a large amount of registers among sub-circuits for partitioning the given sequential circuits. In this paper, we propose an improved TMFPGA architecture to simplify the precedence constraints so that the number of the registers among sub-circuits can be reduced for sequential circuits partitioning. To demonstrate the practicability of the architecture, we also present a greedy algorithm to minimize the maximum number of the registers. Experimental results demonstrate the effectives of the algorithm. <\/jats:p>","DOI":"10.1142\/s0218126613500333","type":"journal-article","created":{"date-parts":[[2013,4,24]],"date-time":"2013-04-24T11:59:48Z","timestamp":1366804788000},"page":"1350033","source":"Crossref","is-referenced-by-count":0,"title":["IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS"],"prefix":"10.1142","volume":"22","author":[{"given":"CHI-CHOU","family":"KAO","sequence":"first","affiliation":[{"name":"Department of Computer Science and Information Engineering, National University of Tainan, Tainan, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"YEN-TAI","family":"LAI","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2013,5,9]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/56320"},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.36"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00050-3"},{"key":"rf7","volume-title":"Computer Organization and Architecture: Designing for Performance","author":"Stallings W.","year":"2003"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.34"},{"key":"rf10","first-page":"66","volume":"58","author":"Gould J.","year":"2006","journal-title":"Xcell J."},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044121"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1109\/92.863618"},{"key":"rf20","doi-asserted-by":"publisher","DOI":"10.1109\/43.952745"},{"key":"rf21","first-page":"278","volume":"22","author":"Mak W. K.","year":"2003","journal-title":"IEEE Trans. Comput.-Aided Design Integr. Circuit Syst."},{"key":"rf22","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2009.2038998"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126613500333","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T13:13:30Z","timestamp":1565183610000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126613500333"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,9]]},"references-count":11,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2013,5,9]]},"published-print":{"date-parts":[[2013,6]]}},"alternative-id":["10.1142\/S0218126613500333"],"URL":"https:\/\/doi.org\/10.1142\/s0218126613500333","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,5,9]]}}}