{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T09:17:18Z","timestamp":1648545438523},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"07","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2013,8]]},"abstract":"<jats:p> As semiconductor technologies scale down to deep sub-micron dimensions, transient faults will soon become a critical reliability concern. Due to their prohibitive costs, traditional high-end solutions are unacceptable for the mainstream commodity market. This paper presents FTPIPE, a hybrid software\/hardware solution, which provides sufficient fault coverage with affordable overhead for single-threaded programs running on commodity systems. Leveraging existing exception mechanisms with minor modifications to handle exception-causing faults, FTPIPE focuses on tolerating silent data corruptions by using compile-time analysis and performing selective instruction replication in a modern superscalar pipeline extended with minimal hardware overhead. Unlike existing instruction replication-based solutions, which detect faults by synchronous checks, the FTPIPE platform has exploited a novel hybrid synchronous\/asynchronous check method for the replicated instructions. In this manner, better performance can be obtained without degradation of fault coverage. By synchronous checks, the validation of the result of a replicated instruction must be finished before it is committed, whereas such a guarantee is not required by an asynchronous check. Evaluation using a set of nine programs from the Mibench benchmark suite demonstrates that FTPIPE can tolerate 89.8% of transient faults under a modest performance overhead of 20.1%. <\/jats:p>","DOI":"10.1142\/s0218126613500588","type":"journal-article","created":{"date-parts":[[2013,7,17]],"date-time":"2013-07-17T08:05:32Z","timestamp":1374048332000},"page":"1350058","source":"Crossref","is-referenced-by-count":1,"title":["IMPLEMENTING LOW-COST FAULT TOLERANCE VIA HYBRID SYNCHRONOUS\/ASYNCHRONOUS CHECKS"],"prefix":"10.1142","volume":"22","author":[{"given":"JIANLI","family":"LI","sequence":"first","affiliation":[{"name":"School of Computer, National University of Defense Technology, Changsha, Hunan 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"QINGPING","family":"TAN","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology, Changsha, Hunan 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"LANFANG","family":"TAN","sequence":"additional","affiliation":[{"name":"School of Computer, National University of Defense Technology, Changsha, Hunan 410073, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2013,8,19]]},"reference":[{"key":"rf1","volume-title":"SER \u2013 History, Trends and Challenges: A Guide for designing with Memory ICs","author":"Ziegler J.","year":"2004"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/24.994913"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1049\/iet-sen.2011.0135"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0038"},{"key":"rf26","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126613500588","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T16:06:27Z","timestamp":1565193987000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126613500588"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":5,"journal-issue":{"issue":"07","published-online":{"date-parts":[[2013,8,19]]},"published-print":{"date-parts":[[2013,8]]}},"alternative-id":["10.1142\/S0218126613500588"],"URL":"https:\/\/doi.org\/10.1142\/s0218126613500588","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,8]]}}}