{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T18:28:44Z","timestamp":1761676124908},"reference-count":14,"publisher":"World Scientific Pub Co Pte Lt","issue":"02","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,2]]},"abstract":"<jats:p> Steganography has become an important method for concealed communication especially through image files. Recent proposed steganographic methods employ multiple levels of complex techniques. Hence, there is an increasing significance for hardware implementation and its performance metrics. The objective of this article is to analyze and model the performance of FPGA hardware implementations of several spatial steganography methods, including: least significant bit (LSB), random LSB, mix-bit LSB and texture method. This paper presents innovative models to estimate energy-to-embed-secret-bit, peak signal-to-noise-ratio (PSNR) energy cost, power and resources in complex systems. Examining the performance results of the FPGA implementations shows that embedding misalignment degrades the performance, and random embedding increases resources by 43% and power by 13%. Furthermore, the mix-bit method has the best results in terms of balancing the energy consumption and PSNR. Moreover, the accuracy of the model to predict the energy to embed a single secret bit is 2%, and the accuracy of the model to predict complex system performance is 1% for hardware resources and 16.6% for power. <\/jats:p>","DOI":"10.1142\/s0218126614500182","type":"journal-article","created":{"date-parts":[[2013,12,16]],"date-time":"2013-12-16T03:46:04Z","timestamp":1387165564000},"page":"1450018","source":"Crossref","is-referenced-by-count":16,"title":["ANALYSIS AND MODELING OF FPGA IMPLEMENTATIONS OF SPATIAL STEGANOGRAPHY METHODS"],"prefix":"10.1142","volume":"23","author":[{"given":"BASSAM J.","family":"MOHD","sequence":"first","affiliation":[{"name":"Computer Engineering Department, Hashemite University, Zarqa 13115, Jordan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"THAIER","family":"HAYAJNEH","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, Hashemite University, Zarqa 13115, Jordan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"SA'ED","family":"ABED","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, Hashemite University, Zarqa 13115, Jordan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"AWNI","family":"ITRADAT","sequence":"additional","affiliation":[{"name":"Computer Engineering Department, Hashemite University, Zarqa 13115, Jordan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2014,2,26]]},"reference":[{"key":"rf1","first-page":"26","volume":"2","author":"Johnson N. F.","journal-title":"IEEE Comput."},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sigpro.2009.08.010"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/MSECP.2003.1203220"},{"key":"rf8","first-page":"17","volume":"4","author":"Amirtharajan R.","journal-title":"Int. J. Comput. Appl."},{"key":"rf9","author":"Zhang X.","journal-title":"Mobile Networks Appl."},{"key":"rf16","author":"Varsaki E.","journal-title":"Signal, Image Video Process."},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1016\/0031-3203(95)00067-4"},{"key":"rf19","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2002.1017623"},{"key":"rf20","volume-title":"Digital Image Processing","author":"Gonzalez R.","year":"2008"},{"key":"rf21","first-page":"24","volume":"18","author":"Sundararaman R.","journal-title":"Int. J. Comput. Appl."},{"key":"rf22","doi-asserted-by":"publisher","DOI":"10.3923\/jas.2012.201.210"},{"key":"rf25","doi-asserted-by":"publisher","DOI":"10.1109\/TIP.2005.860338"},{"key":"rf26","unstructured":"N.\u00a0Weste and D.\u00a0Harris, CMOS VLSI Design: A Circuit and Systems Perspective, 4th edn. (Addison-Wesley, Boston, 2011)\u00a0pp. 200\u2013204."},{"key":"rf27","doi-asserted-by":"publisher","DOI":"10.1007\/s10922-011-9219-8"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126614500182","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T15:00:50Z","timestamp":1565103650000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126614500182"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":14,"journal-issue":{"issue":"02","published-online":{"date-parts":[[2014,2,26]]},"published-print":{"date-parts":[[2014,2]]}},"alternative-id":["10.1142\/S0218126614500182"],"URL":"https:\/\/doi.org\/10.1142\/s0218126614500182","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,2]]}}}