{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T09:12:50Z","timestamp":1648717970349},"reference-count":5,"publisher":"World Scientific Pub Co Pte Lt","issue":"04","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,4]]},"abstract":"<jats:p> In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-\u03bcm CMOS technology and the current source block occupies less than 0.5 mm<jats:sup>2<\/jats:sup>. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is \u00b1 0.3 LSB and \u00b1 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency. <\/jats:p>","DOI":"10.1142\/s0218126614500534","type":"journal-article","created":{"date-parts":[[2014,1,27]],"date-time":"2014-01-27T03:15:21Z","timestamp":1390792521000},"page":"1450053","source":"Crossref","is-referenced-by-count":1,"title":["A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION"],"prefix":"10.1142","volume":"23","author":[{"given":"FAN","family":"XIA","sequence":"first","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P. R. China"}]},{"given":"YIQIANG","family":"ZHAO","sequence":"additional","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P. R. China"}]},{"given":"GONGYUAN","family":"ZHAO","sequence":"additional","affiliation":[{"name":"School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, P. R. China"}]}],"member":"219","published-online":{"date-parts":[[2014,4,15]]},"reference":[{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/4.890297"},{"key":"rf6","first-page":"869","volume":"1","author":"Heebae H.","journal-title":"Circuit and Syst."},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126611007566"},{"key":"rf12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164302"},{"key":"rf13","first-page":"1948","volume":"33","author":"Lin C.-H.","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126614500534","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,7]],"date-time":"2019-08-07T08:59:32Z","timestamp":1565168372000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126614500534"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":5,"journal-issue":{"issue":"04","published-online":{"date-parts":[[2014,4,15]]},"published-print":{"date-parts":[[2014,4]]}},"alternative-id":["10.1142\/S0218126614500534"],"URL":"https:\/\/doi.org\/10.1142\/s0218126614500534","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}