{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T19:49:02Z","timestamp":1648756142047},"reference-count":10,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,6]]},"abstract":"<jats:p> This paper presents an asynchronous instruction cache memory for average-case performance, rather than worst-case performance. Even though the proposed instruction cache design is based on a fixed delay model, it can achieve high throughput by employing a new memory segmentation technique that divides cache memory cell arrays into multiple memory segments. The conventional bit-line memory segmentation divides a whole memory system into multiple segments so that all memory segments have the same size. On the contrary, we propose a new bit-line segmentation technique for the cache memory which consists of multiple segments but all the memory segments have the same delay bound for themselves. We use the resister-capacitor (R-C) modeling of bit-line delay for content addressable memory\u2013random access memory (CAM\u2013RAM) structure in a cache in order to estimate the total bit-line delay. Then, we decide the number of segments to trade-off between the throughput and complexity of a cache system. We synthesized a 128 KB cache memory consisting of various segments from 1 to 16 using Hynix 0.35-\u03bcm CMOS process. From the simulation results, our implementation with dividing factor 4 and 16 can reduce the average cache access time to 28% and 35% when compared to the non-segmented counterpart system. It also shows that our implementation can reduce the average cache access time by 11% and 17% when compared to the bit-line segmented cache that consists of the same number of segments that have the same size. <\/jats:p>","DOI":"10.1142\/s0218126614500637","type":"journal-article","created":{"date-parts":[[2014,2,6]],"date-time":"2014-02-06T02:39:00Z","timestamp":1391654340000},"page":"1450063","source":"Crossref","is-referenced-by-count":1,"title":["ASYNCHRONOUS INSTRUCTION CACHE MEMORY FOR AVERAGE-CASE PERFORMANCE"],"prefix":"10.1142","volume":"23","author":[{"given":"JE-HOON","family":"LEE","sequence":"first","affiliation":[{"name":"Division of Electronics and Information Communication Engineering, Kangwon Nat'l University, 1, Joongang-ro, Samcheok, Gangwon 245-711, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"HYUN GUG","family":"CHO","sequence":"additional","affiliation":[{"name":"Department of Optometry, Kangwon Nat'l University, 1, Joongang-ro, Samcheok, Gangwon, 245-711, Republic of Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"219","published-online":{"date-parts":[[2014,5,8]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1109\/5.362752"},{"key":"rf5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.28"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008054"},{"key":"rf7","doi-asserted-by":"publisher","DOI":"10.1587\/elex.5.87"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.E94.D.1547"},{"key":"rf9","first-page":"93","volume":"8","author":"Rani M. J.","year":"2012","journal-title":"Eur. J. Sci. Res."},{"key":"rf10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2032916"},{"key":"rf11","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(93)90032-8"},{"key":"rf16","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126612500570"},{"key":"rf18","doi-asserted-by":"publisher","DOI":"10.1109\/54.914617"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126614500637","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T19:51:38Z","timestamp":1565121098000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126614500637"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,8]]},"references-count":10,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2014,5,8]]},"published-print":{"date-parts":[[2014,6]]}},"alternative-id":["10.1142\/S0218126614500637"],"URL":"https:\/\/doi.org\/10.1142\/s0218126614500637","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,5,8]]}}}