{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T14:08:47Z","timestamp":1649081327261},"reference-count":6,"publisher":"World Scientific Pub Co Pte Lt","issue":"05","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J CIRCUIT SYST COMP"],"published-print":{"date-parts":[[2014,6]]},"abstract":"<jats:p> A novel 1\/4-rate clock phase detector (PD) structure for phase locked loop (PLL)-based clock and data recovery (CDR) is proposed. In this topology, the retimed data is generated within the circuit and no extra circuit is required. Furthermore, the error and reference signals are independent of delay time through gates and thus, no extra replica circuit is needed to compensate such delay. Designed in a 0.18-\u03bcm CMOS technology, the proposed 10 Gb\/s PD consumes 30 mA from a 1.8 V supply, resulting in a lower power consumption for high-speed applications compared to conventional topologies. <\/jats:p>","DOI":"10.1142\/s0218126614500728","type":"journal-article","created":{"date-parts":[[2014,2,26]],"date-time":"2014-02-26T12:59:45Z","timestamp":1393419585000},"page":"1450072","source":"Crossref","is-referenced-by-count":3,"title":["A 1\/4-RATE LINEAR PHASE DETECTOR FOR HIGH SPEED PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT"],"prefix":"10.1142","volume":"23","author":[{"given":"SOMAYEH","family":"ADIBIFARD","sequence":"first","affiliation":[{"name":"Electrical Engineering Department, Shahed University, Tehran, Iran"}]},{"given":"SEYYED HASSAN","family":"MOUSAVI","sequence":"additional","affiliation":[{"name":"\u00c9cole de Technologie Sup\u00e9rieure, Universit\u00e9 du Qu\u00e9bec, Montr\u00e9al, Qu\u00e9bec, H3C 1K3, Canada"}]},{"given":"SOHEYL","family":"ZIABAKHSH","sequence":"additional","affiliation":[{"name":"\u00c9cole de Technologie Sup\u00e9rieure, Universit\u00e9 du Qu\u00e9bec, Montr\u00e9al, Qu\u00e9bec, H3C 1K3, Canada"}]},{"given":"MUSTAPHA C. E.","family":"YAGOUB","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Canada"}]}],"member":"219","published-online":{"date-parts":[[2014,5,8]]},"reference":[{"key":"rf1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2269616"},{"key":"rf2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883334"},{"key":"rf3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818566"},{"key":"rf4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.813292"},{"key":"rf6","doi-asserted-by":"publisher","DOI":"10.1109\/4.918913"},{"key":"rf8","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2013.0023"}],"container-title":["Journal of Circuits, Systems and Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.worldscientific.com\/doi\/pdf\/10.1142\/S0218126614500728","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,6]],"date-time":"2019-08-06T19:51:56Z","timestamp":1565121116000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.worldscientific.com\/doi\/abs\/10.1142\/S0218126614500728"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,8]]},"references-count":6,"journal-issue":{"issue":"05","published-online":{"date-parts":[[2014,5,8]]},"published-print":{"date-parts":[[2014,6]]}},"alternative-id":["10.1142\/S0218126614500728"],"URL":"https:\/\/doi.org\/10.1142\/s0218126614500728","relation":{},"ISSN":["0218-1266","1793-6454"],"issn-type":[{"value":"0218-1266","type":"print"},{"value":"1793-6454","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,5,8]]}}}